NAND02GW3B2DZA6E Micron Technology Inc, NAND02GW3B2DZA6E Datasheet

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... SLC NAND flash memories Features High density NAND flash memory – Gbits of memory array – Cost-effective solution for mass storage applications NAND interface – x16 bus width – Multiplexed address/data Supply voltage: 1 device Page size – x8 device: (2048 + 64 spare) bytes – ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.16 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 46 10 Maximum ratings ...

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Contents 11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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NAND02G-BxD List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. A write protect pin is available to provide hardware protection against program and erase operations ...

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... Table 31: Ordering information Timings Sequential Random Page Block access access Program Erase time (min) time (max) (typ) (typ µs 200 µs 1 NAND Flash Memory Array Page Buffer Cache Register Y Decoder I/O Buffers & Latches I/O0-I/O7 (x8/x16) I/O8-I/O15 (x16) Package VFBGA63 TSOP48 VFBGA63 AI13166b ...

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... Ready/Busy (open-drain output) W Write Enable WP Write Protect V Supply voltage DD V Ground SS NC Not connected internally DU Do not use V DD I/O0-I/O7 (x8/x16) E I/O8-I/O15 (x16 NAND FLASH Function Description AI13167b Direction Input/output Input/output Input Input Input Input Output Input Input Power supply Ground – ...

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... Description Figure 3. TSOP48 connections 10/ NAND FLASH NAND02G-BxD I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI13168b ...

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NAND02G-BxD Figure 4. VFBGA63 connections (top view through package ...

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... In x16 devices, the pages are split into a 1024-word main area and a spare area of 32 words. Refer to Bad blocks In the x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad blocks, which are blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. ...

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NAND02G-BxD Figure 5. Memory array organization Plane = 1024 blocks, block = 64 pages, page = 2112 bytes (2048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes 2048 bytes plane = 2048 blocks, block = 64 ...

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Signals description 3 Signals description See Figure 2: Logic connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/outputs input the selected address, output the data during a read operation, or input a command or data during a write ...

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NAND02G-BxD 3.7 Write Enable (W) The Write Enable input, W, controls writing to the command interface, input address, and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery ...

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Bus operations 4 Bus operations There are six standard bus operations that control the memory, as described in this section. See Table 4: Bus operations Typically, glitches of less than Chip Enable, Write Enable, and Read Enable ...

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NAND02G-BxD If the Read Enable pulse frequency is lower then 33 MHz (t output data is latched on the rising edge of Read Enable signal (see For higher frequencies (t used. In this mode, Data Output bus operations are valid ...

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Bus operations Table 6. Address insertion (x16 devices) Bus I/O7 (1) cycle A18 th 4 A26 Any additional address input cycles are ignored. Table 7. Address ...

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NAND02G-BxD 5 Command set All bus write operations sent to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the command Latch Enable signal ...

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Device operations 6 Device operations This section provides details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode, the read command must be issued (see 6.1.1 ...

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NAND02G-BxD Figure 6. Read operations I/O Address Input 00h Command Code tBLBH1 30h Data Output (sequentially) Command Busy Code Device operations ai12469 21/67 ...

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Device operations Figure 7. Random data output during sequential data output tBLBH1 (Read Busy time Address 30h I/O 00h Inputs Cmd Cmd Code Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area 6.2 Cache ...

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NAND02G-BxD After the Sequential Cache Read or Random Cache Read command has been issued, the Ready/Busy signal goes Low and the status register bits are set to SR5 =' 0' and SR6 ='0'. This is for a period of cache ...

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Device operations 6.3 Page program The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however, the device does support random input within a page recommended to ...

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NAND02G-BxD Figure 10. Page program operation RB I/O 80h Page Program Setup Code Figure 11. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd code 5 Add cycles Row Add 1,2,3 Col Add 1,2 ...

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Device operations 6.4 Multiplane page program The devices support multiplane page program operations, which enables the programming of two pages in parallel, one in each plane. A multiplane page program operation requires the following two steps: 1. The first step ...

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NAND02G-BxD Figure 12. Multiplane page program waveform RB 1 I/O Address inputs 80h A0-A11 = Valid Page Program setup code A12-A17 = set to 'Low' A18 = set to 'Low' A19-A28 = set to 'Low' 1) The same row address, ...

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Device operations The NAND02G-BxD device features automatic EDC (error detection code) during a copy back operation. Consequently longer required to use an external ECC to detect copy back operation errors. Read error occurrences can be detected by ...

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NAND02G-BxD Figure 15. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB 6.6 Multiplane copy back program In addition to multiplane page program, the NAND02G-BxD device supports multiplane ...

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Device operations Figure 16. Multiplane copy back program Read Read code code Add. 5 I/O 35h 00h 00h cycles Col. Add Row Add Source address on 1st plane Source address on 2nd plane tBLBH1 (Read ...

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NAND02G-BxD 6.7 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists of ...

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Device operations 6.8 Multiplane block erase The multiplane block erase operation allows the erasure of two blocks in parallel, one in each plane. This operation consists of the following three steps (refer to erase bus cycles are required ...

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NAND02G-BxD 6.9 Error detection code (EDC) The EDC is performed automatically during all copy back operations. It starts immediately after the device becomes busy. The EDC detects 1 single bit error per EDC unit. Each EDC unit has a density ...

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Device operations Table 11. Address definition for EDC units (x16 devices) EDC unit Area name 1st 264-word EDC unit 2nd 264-word EDC unit 3rd 264-word EDC unit 4th 264-word EDC unit 6.10 Reset The Reset command is used to reset ...

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NAND02G-BxD 6.11.2 P/E/R controller and cache ready/busy bit (SR6) Status register bit SR6 has two different functions depending on the current operation. During cache operations, SR6 acts as a Cache Ready/Busy bit, which indicates whether the cache register is ready ...

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... Device operations 6.12 Read status enhanced In NAND flash devices with multiplane architecture possible to independently read the status register of a single plane using the Read Status Enhanced command. If the error bit of the status register, SR0, reports an error during or after a multiplane operation, the Read Status Enhanced command is used to know which of the two planes contains the page that failed the operation ...

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NAND02G-BxD 6.14 Read electronic signature The devices contain a manufacturer code and device code. The following three steps are required to read these codes: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One bus ...

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Device operations Table 16. Electronic signature byte 4 I/O I/O1-I/O0 (without spare area) Spare area size I/O2 (byte/512 byte) Minimum sequential access I/O7, I/O3 I/O5-I/O4 (without spare area) I/O6 Table 17. Electronic signature byte 5 I/O I/O1 - I/O0 I/O3 ...

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... Read ONFI signature To recognize NAND flash devices that are compatible with the ONFI 1.0 command set, the Read Electronic Signature command can be issued, followed by an address of 20h. The next four bytes output is the ONFI signature, which is the ASCII encoding of the ‘ONFI’ word. ...

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Device operations Table 19. Parameter page data structure Byte O/M 0-3 4-5 6-7 8-9 10-31 32-43 44-63 64 65-66 67-79 80-83 84-85 86-89 90-91 92-95 40/67 (1) Parameter page signature – Byte 0: 4Fh, ‘O’ M – Byte 1: 4Eh, ...

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NAND02G-BxD Table 19. Parameter page data structure (continued) Byte O/M 96-99 100 101 102 103-104 105-106 107 108-109 110 111 112 113 114 115-127 128 (1) M Number of blocks per logical unit (LUN) M Number of logical units (LUNs) ...

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Device operations Table 19. Parameter page data structure (continued) Byte O/M 129-130 131-132 133-134 135-136 137-138 139-163 164-165 166-253 254-255 256-511 512-767 768 optional mandatory. 42/67 (1) Timing mode support Bit 6 to bit 15 ...

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... This section provides information on the software algorithms that Numonyx recommends implementing to manage the bad blocks and extend the lifetime of the NAND device. NAND flash memories are programmed and erased by Fowler-Nordheim tunnelling using high voltage. Exposing the device to high voltage for extended periods damages the oxide layer ...

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... Software algorithms 8.2 NAND flash memory failure modes Over the lifetime of the device bad blocks may develop. To implement a highly reliable system, the possible failure modes must be considered. Program/erase failure In this case, the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified because attempts to program or erase them gives errors in the status register ...

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... Error correction code Users must implement an error correction code (ECC) to identify and correct errors in the data stored in NAND flash memories. The ECC implemented must be able to correct 1 bit for every 512 bytes. Sensible data stored in the spare area must be covered by ECC as well. ...

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... Multiplane program busy time (t IPBSY Multiplane erase busy time (t IEBSY Cache read busy time (t ) RCBSY Program/erase cycles per block (with ECC) Data retention 46/67 Min 100,000 10 NAND02G-BxD NAND flash Typ Max 200 700 200 700 250 800 1 2.5 0 ...

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NAND02G-BxD 10 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating ...

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... Input/output capacitances double in stacked devices. 48/67 Parameter 1.8 V device ) 3 V device ) Grade 6 A 1.8 V device ) (1 TTL GATE device ref (1) Parameter Test condition (2) IL and C are not 100% tested. IN I/O NAND02G-BxD NAND flash Units Min Max 1.7 1.95 V 2.7 3.6 –40 85 ° 8.35 kΩ Typ ...

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... Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently executing different operations. NAND Flash C L GND ...

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DC and AC parameters Table 26. DC characteristics (3 V devices) Symbol Parameter I DD1 Operating I current DD2 I DD3 Standby current (TTL) I DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current ...

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NAND02G-BxD Table 28. AC Characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t BLBH2 PROG t ...

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DC and AC parameters electronic signature the time from W rising edge during the final address cycle to W rising edge during the first data cycle. ADL 4. During a program/erase enable operation, t ...

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NAND02G-BxD Figure 24. Address latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH (AL Setup time) tWHALL (AL Hold time) AL tDVWH (Data Setup time) Adrress I/O cycle 1 Figure 25. Data input latch AC waveforms ...

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DC and AC parameters Figure 26. Sequential data output after read AC waveforms E R tRLQV (R Accesstime) I/O tBHRL Low Low High applicable for frequencies lower than 33 ...

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NAND02G-BxD Figure 28. Read status register or read EDC status register AC waveform CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 29. Read status enhanced waveform I/O 0-7 78h Address 1 tCLLRL tWHCLL ...

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DC and AC parameters Figure 30. Read electronic signature AC waveform I/O 90h Read Electronic Signature Command 1. Refer to Table 14 for the values of the manufacturer and device codes, and to information contained ...

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NAND02G-BxD Figure 32. Page read operation AC waveform CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N 30h ...

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DC and AC parameters Figure 33. Page program AC waveform CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code 58/67 tWLWL tWHWH Add.N Add.N Add.N N cycle ...

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NAND02G-BxD Figure 34. Block erase AC waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 35. Reset AC waveform I/O FFh ...

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DC and AC parameters Figure 36. Program/erase enable waveform W tVHWH WP RB I/O 80h Program setup Figure 37. Program/erase disable waveform W tVLWH WP High RB I/O Program disable Figure 38. Read parameter page waveform ...

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NAND02G-BxD 11.1 Ready/busy signal electrical characteristics Figure 40, Figure 39 signal. The value required for the resistor R This is an example for 3 V devices: where I is the sum of the input currents of all the devices tied ...

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DC and AC parameters Figure 41. Resistor value versus waveform timings for ready/busy signal °C. 11.2 Data protection The Numonyx NAND devices are designed to guarantee data protection during power transitions detection circuit disables ...

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NAND02G-BxD 12 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance ...

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Package mechanical Figure 44. VFBGA63 1.05 mm, 0.8 mm pitch, package outline FD1 BALL "A1" Drawing is not to scale Table 30. VFBGA63 1.05 mm, 0.8 mm ...

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... NAND02G-BxD 13 Ordering information Table 31. Ordering information scheme Example: Device type NAND flash memory Density 02G = 2 Gbits Operating voltage 2 1 Bus width x16 Family identifier B = 2112-byte page Device options 2 = Chip Enable ‘don't care’ enabled A = Automotive testing Product version ...

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Revision history 14 Revision history Table 32. Document revision history Date 07-Sep-2007 13-Feb-2008 03-Apr-2008 24-Apr-2008 12-Sep-2008 11-Mar-2009 16-Feb-2010 66/67 Revision 1 Initial release. Document status promoted from target specification to preliminary data. Modified: Figure 12: Multiplane page program Figure 16: ...

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... Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...