SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 106

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
Table 88:
[1]
Table 89:
[1]
Table 90:
[1]
X port signal definitions text slicer
Video data limited to range 1 to 254
Video data limited to range 8 to 247
Dword byte swap, influences serial output timing
D0 D1 D2 D3
D1 D0 D3 D2
D2 D3 D0 D1
D3 D2 D1 D0
I port reference signal polarities
IDQ at default polarity (1 = active)
IDQ is inverted
IGPH at default polarity (1 = active)
IGPH is inverted
IGPV at default polarity (1 = active)
IGPV is inverted
IGP1 at default polarity
IGP1 is inverted
IGP0 at default polarity
IGP0 is inverted
Function
See subaddress 84h: IDG11 and IDG10
See subaddress 84h: IDG01 and IDG00
I port signal definitions
I port data output inhibited
Only video data is transferred
Only text data is transferred (no EAV, SAV will occur)
Text and video data is transferred, text has priority
X = don’t care.
X = don’t care.
X = don’t care.
X port signal definitions text slicer; global set 85h[7:5]
I port reference signal polarities; global set 85h[4:0]
I port FIFO flag control and arbitration; global set 86h[7:4]
FF 00 00 SAV C
00 FF SAV 00 Y0 C
00 SAV FF 00 C
SAV 00 00 FF Y1 C
Rev. 03 — 17 January 2006
B
R
0 Y0 C
0 Y1 C
B
R
0 Y1 C
0 Y0 C
R
B
0 Y1
0 Y0
R
B
0
0
Control bits D4 to D0
IG0P
X
X
X
X
X
X
X
X
0
1
PAL/NTSC/SECAM video decoder
IG1P
X
X
X
X
X
X
0
1
X
X
Control bits D7 to D4
VITX1
X
X
X
X
0
0
1
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
[1]
Control bits D7 to D5
ISWP1
X
X
0
0
1
1
IRVP
X
X
X
X
0
1
X
X
X
X
[1]
VITX0
X
X
X
X
0
1
0
1
[1]
SAA7114
ISWP0
X
X
0
1
0
1
IRHP
X
X
0
1
X
X
X
X
X
X
IDG02 IDG12
X
X
0
1
X
X
X
X
106 of 144
ILLV
0
1
X
X
X
X
IDQP
0
1
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X