ADSP-2115KP-80 Analog Devices Inc, ADSP-2115KP-80 Datasheet - Page 47

• Manufacturer Part Number: ADSP-2115KP-80
• Manufacturer: Analog Devices Inc

Specifications of ADSP-2115KP-80

• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 1.5KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

REV. B
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
t
t
Switching Characteristic:
t
t
t
t
NOTES
1
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
requires a pulse width greater than 10 ns.
If BR meets the t
BH
BS
SD
SDB
SE
SEC
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR Disable to BG Low
BG High to DMS, PMS, BMS, RD, WR Enable
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
BS
and t
BH
PMS, DMS
BMS, RD
CLKOUT
CLKOUT
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
WR
BG
BR
t
1
SD
t
BH
1
t
BS
t
SDB
Figure 41. Bus Request/Grant
–47–
10.24 MHz
Min
29.4
44.4
0
0
14.4
Max
44.4
t
SE
t
SEC
Frequency
Dependency
Min
0.25t
0.25t
0.25t
CK
CK
CK
+ 5
+ 20
– 10
Max
0.25t
ADSP-21xx
CK
+ 20
Unit
ns
ns
ns
ns
ns
ns