PCA9536D,118 NXP Semiconductors, PCA9536D,118 Datasheet - Page 7

IC I/O EXPANDER I2C 4B 8SOIC

PCA9536D,118

Manufacturer Part Number
PCA9536D,118
Description
IC I/O EXPANDER I2C 4B 8SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9536D,118

Package / Case
8-SOIC (3.9mm Width)
Interface
I²C, SMBus
Number Of I /o
4
Interrupt Output
No
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9536
Number Of Lines (input / Output)
4.0 / 4.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
200 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I2C, SMBus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
4.0
Number Of Output Lines
4.0
Output Current
50 mA
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-3615 - DEMO BOARD I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1835-2
935277415118
PCA9536D-T
NXP Semiconductors
PCA9536_5
Product data sheet
6.4 Device address
6.5 Bus transactions
Data is transmitted to the PCA9536 registers using the Write mode as shown in
and
Figure 9
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
Fig 5.
Fig 6.
write configuration
Figure
write polarity
shift register
shift register
shift register
write pulse
read pulse
data from
data from
data from
and
Remark: At power-on reset, all registers return to default values.
Simplified schematic of IO0 to IO3
PCA9536 device address
pulse
pulse
8. Data is read from the PCA9536 registers using the Read mode as shown in
Figure
configuration
register
D
CK
FF
10. These devices do not implement an auto-increment function, so
Rev. 05 — 25 January 2010
Q
Q
1
output port
register
D
CK
0
FF
slave address
Q
0
fixed
0
input port
register
polarity inversion
register
0
D
CK
D
CK
FF
FF
0
Q
Q
002aab853
1
4-bit I
R/W
Q1
2
C-bus and SMBus I/O port
Q2
100 kΩ
PCA9536
© NXP B.V. 2010. All rights reserved.
output port
register data
V
IO0 to IO3
V
input port
register data
polarity inversion
register data
DD
SS
002aab852
Figure 7
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