PCA9506DGG,512 NXP Semiconductors, PCA9506DGG,512 Datasheet - Page 8
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PCA9506DGG,512
Manufacturer Part Number
PCA9506DGG,512
Description
IC I/O EXPANDER I2C 40B 56TSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9505DGG112.pdf
(34 pages)
Specifications of PCA9506DGG,512
Package / Case
56-TSSOP
Interface
I²C
Number Of I /o
40
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9506
Number Of Lines (input / Output)
40.0 / 40.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
500 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5.5 V
Logic Type
I/O Expander
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
40.0
Number Of Output Lines
40.0
Output Current
50 mA
Output Voltage
5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3354-5
935280798512
PCA9506DGG
935280798512
PCA9506DGG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9506DGG,512
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
PCA9505_9506
Product data sheet
The lowest 6 bits are used as a pointer to determine which register will be accessed. The
registers are:
If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the
5 register banks sequentially.
If more than 5 bytes of data are written and AI = 1, previous data in the selected registers
will be overwritten. Reserved registers are skipped and not accessed (refer to
If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not
incremented after data is read or written. During a read operation, the same register bank
is read each time. During a write operation, data is written to the same register bank each
time.
Only a Command register code with the 5 least significant bits equal to the 25 allowable
values as defined in
be accessed for proper device functionality. At power-up, this register defaults to 0x80,
with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.
During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and
IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since
these are read-only registers.
•
•
•
•
•
IP: Input Port registers (5 registers)
OP: Output Port registers (5 registers)
PI: Polarity Inversion registers (5 registers)
IOC: I/O Configuration registers (5 registers)
MSK: Mask interrupt registers (5 registers)
All information provided in this document is subject to legal disclaimers.
Table 3
Rev. 4 — 3 August 2010
are valid. Reserved or undefined command codes must not
40-bit I
2
C-bus I/O port with RESET, OE and INT
PCA9505/06
© NXP B.V. 2010. All rights reserved.
Table
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3).