PCA9534PW,118 NXP Semiconductors, PCA9534PW,118 Datasheet - Page 7

• Manufacturer Part Number: PCA9534PW,118
• Description: IC I/O EXPANDER I2C 8B 16TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9534PW,118

• Package / Case: 16-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9534
• Number Of Lines (input / Output): 8.0 / 8.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 200 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Current: 50 mA
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1834-2; 935275051118; PCA9534PW-T

NXP Semiconductors
PCA9534_3
Product data sheet
Fig 6. Simplified schematic of IO0 to IO7
Remark: At power-on reset, all registers return to default values.
write configuration
write polarity
shift register
shift register
shift register
write pulse
read pulse
data from
data from
data from
6.5 Device address
6.6 Bus transactions
pulse
pulse
Data is transmitted to the PCA9534 registers using the Write mode as shown in
and
Figure 10
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
Fig 7. PCA9534 device address
configuration
register
D
CK
Figure
FF
Q
Q
and
9. Data is read from the PCA9534 registers using the Read mode as shown in
Figure
output port
register
D
CK
FF
Rev. 03 — 6 November 2006
11. These devices do not implement an auto-increment function, so
Q
8-bit I
0
input port
register
polarity inversion
register
D
CK
D
CK
2
C-bus and SMBus low power I/O port with interrupt
1
FF
FF
fixed
Q
Q
slave address
0
0
A2
selectable
hardware
Q1
A1
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A0 R/W
Q2
output port
register data
V
IO0 to IO7
V
input port
register data
to INT
polarity inversion
register data
DD
SS
PCA9534
© NXP B.V. 2006. All rights reserved.
002aac470
Figure 8
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