MCP23S08-E/P Microchip Technology, MCP23S08-E/P Datasheet - Page 4
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MCP23S08-E/P
Manufacturer Part Number
MCP23S08-E/P
Description
IC I/O EXPANDER SPI 8B 18DIP
Manufacturer
Microchip Technology
Specifications of MCP23S08-E/P
Package / Case
18-DIP (0.300", 7.62mm)
Interface
SPI
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
10MHz
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Includes
POR
Logic Family
MCP23S08
Propagation Delay Time
50 ns
Operating Supply Voltage
1.8 V to 5.5 V
Power Dissipation
700 mW
Operating Temperature Range
- 40 C to + 125 C
Input Voltage
1.8 V to 5.5 V
Logic Type
I/O Expander
Maximum Clock Frequency
10 MHz
Maximum Operating Frequency
1.7 MHz
Mounting Style
Through Hole
Output Current
25 mA
Output Voltage
1.8 V to 4.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPAD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
MCP23008/MCP23S08
1.2
The on-chip POR circuit holds the device in reset until
V
the POR circuit (i.e., release the device from reset).
The maximum V
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3
This block handles the functionality of the I
(MCP23008) or SPI (MCP23S08) interface protocol.
The MCP23X08 contains eleven registers that can be
addressed through the serial interface block (Table 1-2):
TABLE 1-2:
1.3.1
The Sequential Operation (SEQOP) bit (IOCON
register) controls the operation of the address pointer.
The address pointer can either be enabled (default) to
allow the address pointer to increment automatically
after each data transfer, or it can be disabled.
When
(IOCON.SEQOP = 0), the address pointer automati-
cally increments to the next address after each byte
is clocked.
When operating in Byte mode (IOCON.SEQOP = 1),
the MCP23X08 does not increment its address
counter after each byte during the data transfer. This
gives the ability to continually read the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes.
DS21919B-page 4
DD
has reached a high enough voltage to deactivate
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
Power-on Reset (POR)
Serial Interface
operating
SEQUENTIAL OPERATION BIT
DD
REGISTER ADDRESSES
rise time is specified in Section 2.0
IODIR
IPOL
GPINTEN
DEFVAL
INTCON
IOCON
GPPU
INTF
INTCAP (Read-only)
GPIO
OLAT
in
Access to:
Sequential
mode
2
C
1.3.2
1.3.2.1
The I
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23008. The operation is ended with a STOP
or RESTART condition being generated by the master.
Data is written to the MCP23008 after every byte
transfer. If a STOP or RESTART condition is
generated during a data transfer, the data will not be
written to the MCP23008.
Byte writes and sequential writes are both supported
by the MCP23008. The MCP23008 increments its
address counter after each ACK during the data
transfer.
1.3.2.2
The I
sequence, as shown in the bottom of Figure 1-1. This
sequence is followed by another control byte (includ-
ing the START condition and ACK) with the R/W bit
equal to a logic 1 (R/W = 1). The MCP23008 then
transmits the data contained in the addressed register.
The sequence is ended with the master generating a
STOP or RESTART condition.
1.3.2.3
For sequential operations (Write or Read), instead of
transmitting a STOP or RESTART condition after the
data transfer, the master clocks the next byte pointed to
by the address pointer (see Section 1.3.1 “Sequential
Operation Bit” for details regarding sequential
operation control).
The sequence ends with the master sending a STOP or
RESTART condition.
The MCP23008 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
1.3.3
1.3.3.1
The SPI Write operation is started by lowering CS. The
Write command (slave address with R/W bit cleared) is
then clocked into the device. The opcode is followed by
an address and at least one data byte.
1.3.3.2
The SPI Read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then clocked into the device. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
2
2
C Write operation includes the control byte and
C Read operation includes the control byte
I
SPI™ INTERFACE
2
C™ INTERFACE
I
I
I
SPI Write Operation
SPI Read Operation
2
2
2
C Write Operation
C Read Operation
C Sequential Write/Read
© 2005 Microchip Technology Inc.