MCP23S18-E/MJ Microchip Technology, MCP23S18-E/MJ Datasheet - Page 25

IC I/O EXPANDER SPI 16B 24QFN

MCP23S18-E/MJ

Manufacturer Part Number
MCP23S18-E/MJ
Description
IC I/O EXPANDER SPI 16B 24QFN
Manufacturer
Microchip Technology
Datasheet

Specifications of MCP23S18-E/MJ

Package / Case
24-QFN
Interface
SPI
Number Of I /o
16
Interrupt Output
Yes
Frequency - Clock
10MHz
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
Interface ICs
Propagation Delay Time
50 ns
Operating Supply Voltage
1.8 V to 5.5 V
Power Dissipation
700 mW
Operating Temperature Range
- 40 C to + 125 C
Input Voltage
1.8 V to 5.5 V
Logic Type
I/O Expander
Maximum Clock Frequency
10 MHz
Maximum Operating Frequency
3.4 MHz
Mounting Style
SMD/SMT
Output Current
400 mA
Output Voltage
0.6 V to 4.8 V
Package
24QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP23S18-E/MJ
Manufacturer:
Maxim
Quantity:
243
1.6.7
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set the corresponding port pin is
internally pulled up with an internal resistor.
REGISTER 1-9:
FIGURE 1-10:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
R/W-0
PU7
400
350
300
250
200
150
100
PULL-UP RESISTOR
CONFIGURATION REGISTER
50
0
PU7:PU0: Controls the internal pull-up resistors on each pin (when configured as an input or output)
<7:0>.
1 = Pull-up enabled.
0 = Pull-up disabled.
1.5
R/W-0
GPIO Pin Internal Pull-up Current vs V
PU6
GPPU – GPIO PULL-UP RESISTOR REGISTER
TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS
2
W = Writable bit
‘1’ = Bit is set
R/W-0
PU5
2.5
R/W-0
PU4
3
V
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
MCP23018/MCP23S18
DD
3.5
R/W-0
PU3
(V)
T = +25°C
4
R/W-0
PU2
T = +85°C
4.5
T = -40°C
x = Bit is unknown
DD
R/W-0
T = +125°C
PU1
5
DS22103A-page 25
R/W-0
5.5
PU0
bit 0

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