PCA9501D,112 NXP Semiconductors, PCA9501D,112 Datasheet - Page 10

• Manufacturer Part Number: PCA9501D,112
• Description: IC I/O EXPANDER I2C 8B 20SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9501D,112

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Includes: EEPROM
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3353-5; 935272364112; PCA9501D

NXP Semiconductors
PCA9501_4
Product data sheet
Fig 15. Random read
Fig 16. Sequential read
SDA
SDA
S
START condition
1
S
START condition
slave address (memory)
7.4.2.2 Random read
7.4.2.3 Sequential read
A5 A4 A3 A2 A1 A0
1
slave address (memory)
A5 A4 A3 A2 A1 A0
The PCA9501’s random read mode allows the address to be read from to be specified by
the master. This is done by performing a dummy write to set the address counter to the
location to be read. The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the acknowledge from the
PCA9501, the master re-issues the START condition and memory slave address with the
R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed location. The master
ceases the transmission by issuing the STOP condition after the eighth bit, omitting the
ninth clock cycle acknowledge.
The PCA9501 sequential read is an extension of either the current address read or
random read. If the master does not issue a STOP condition after it has received the
eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the
address counter and use the next eight cycles to transmit the data from that location. The
master can continue this process to read the contents of the entire memory. Upon
reaching address 255 the counter will return to address 0 and continue transmitting data
until a STOP condition is received. The master ceases the transmission by issuing the
STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge.
Fig 14. Current address read
R/W
0
SDA
R/W
A
acknowledge
from slave
1
S
START condition
A
acknowledge
from slave
1
word address
slave address (memory)
data from memory
A5 A4 A3 A2 A1 A0
Rev. 04 — 10 February 2009
8-bit I
DATA n
acknowledge
from slave
2
acknowledge
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
from master
A
S
START condition
A
R/W
1
1
slave address (memory)
data from memory
A
A5 A4 A3 A2 A1 A0
acknowledge
from slave
DATA n + 1
acknowledge
data from memory
from master
acknowledge
from slave
A
R/W
1
A
data from memory
DATA n + X
data from memory
P
STOP condition
PCA9501
© NXP B.V. 2009. All rights reserved.
002aad298
condition
002aad300
STOP
condition
002aad299
STOP
P
P
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