SAA-XC866-4FRA 5V BE Infineon Technologies, SAA-XC866-4FRA 5V BE Datasheet - Page 76
SAA-XC866-4FRA 5V BE
Manufacturer Part Number
SAA-XC866-4FRA 5V BE
Description
IC MCU 8BIT FLASH PG-TSSOP-38
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAA-XC866-2FRA_BE.pdf
(114 pages)
Specifications of SAA-XC866-4FRA 5V BE
Core Processor
XC800
Core Size
8-Bit
Speed
86MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
38-TFSOP (0.173", 4.40mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With
MCBXC866 - BOARD EVAL FOR INFINEON XC86X
Other names
AX8664FRABEXT
SAA-XC866-4FRA BE
SAA-XC866-4FRA5VBEINTR
SAA-XC866-4FRABEINTR
SAA-XC866-4FRABEINTR
SP000281792
SAA-XC866-4FRA BE
SAA-XC866-4FRA5VBEINTR
SAA-XC866-4FRABEINTR
SAA-XC866-4FRABEINTR
SP000281792
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3.11.2
In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In
theory, this timer could be used in any of its modes. But in practice, it should be set into
auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the
required baud rate. The baud rate is determined by the Timer 1 overflow rate and the
value of SMOD as follows:
3.12
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock
The output frequency in normal divider mode is derived as follows:
Data Sheet
Baud Rate Generation using Timer 1
Normal Divider Mode (8-bit Auto-reload Timer)
f
MOD
that is 1/n of the input clock
Mode 1, 3 baud rate
f
MOD
=
f
DIV
73
=
---------------------------------------------------- -
32 2
×
----------------------------- -
256 STEP
2
×
f
SMOD
DIV
–
×
, where n is defined by 256 - STEP.
1
(
256 TH1
×
f
PCLK
–
Functional Description
)
Figure
SAA-XC866
29). Once the
V1.5, 2010-09
[3.1]
[3.2]
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