A6850KLTR-T Allegro Microsystems Inc, A6850KLTR-T Datasheet - Page 12

• Manufacturer Part Number: A6850KLTR-T
• Description: IC SWITCH INTERFACE 2CHAN 8-SOIC
• Manufacturer: Allegro Microsystems Inc
• Type: Hall Effect Switchr

Specifications of A6850KLTR-T

• Input Type: Voltage
• Output Type: Voltage
• Interface: 2-Wire Serial
• Current - Supply: 5mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Interface Applications: Microprocessors, 2 Wire Hall Effect Sensor IC
• Supply Voltage Range: 4.75V To 26.5V
• Power Dissipation Pd: 52mW
• Operating Temperature Range: -40°C To +125°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 620-1185-2

A6850
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright ©2006-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
9X
0.20
0.41 ±0.10
C
A
8
1
4.90 ±0.10
2
For the latest version of this document, visit our website:
1.27 BSC
L Package, 8-Pin SOIC
0.18
3.90 ±0.10
www.allegromicro.com
+0.08
–0.07
SEATING
PLANE
1.75 MAX
6.00 ±0.20
C
C
Dual Channel Switch Interface IC
A Terminal #1 mark area
B Reference land pattern layout (reference IPC7351
For Reference Only, not for tooling use
(reference JEDEC MS-012 AA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
GAUGE PLANE
0.25 BSC
4° ±4
SEATING PLANE
0.84
0.21 ±0.04
(1.04)
+0.43
–0.44
0.65
1.75
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
B
8
1
PCB Layout Reference View
2
1.27
5.60
12