AD9845BJSTZ Analog Devices Inc, AD9845BJSTZ Datasheet - Page 12

IC CCD SIGNAL PROC 12BIT 48-LQFP

AD9845BJSTZ

Manufacturer Part Number
AD9845BJSTZ
Description
IC CCD SIGNAL PROC 12BIT 48-LQFP
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 12-Bitr
Datasheet

Specifications of AD9845BJSTZ

Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
48-LQFP
Supply Voltage Range
2.7V To 3.6V
Ic Mounting
SMD
Tv / Video Case Style
LFCSP
No. Of Pins
48
Msl
MSL 3 - 168 Hours
Termination Type
SMD
Sample Rate
30MSPS
Data Interface
3-Wire, Serial
Filter Terminals
SMD
Rohs Compliant
Yes
Digital Ic Case Style
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9845BJSTZ
Manufacturer:
AD
Quantity:
560
Part Number:
AD9845BJSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9845BJSTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9845B
HD
VD
HD
VD
PxGA GAIN
PxGA GAIN
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
0 = GAIN0, 1 = GAIN1, 2 = GAIN2
SHP
SHP
HD
VD
HD
VD
0101...
LINE 0
0101...
LINE 0
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323... (ODD).
NOTES
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
3ns MIN
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
0101...
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
LINE 1
1212...
LINE 1
EVEN FIELD
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
5 PIXEL MIN
FRAME N
5 PIXEL MIN
0101...
LINE 2
LINE 2
0101...
LINE M–1
LINE M–1
3ns MIN
GAINX
LINE M
LINE M
–12–
3ns MIN
GAINX
GAIN0
2323...
LINE 0
0101...
3ns MIN
LINE 0
GAIN1
GAIN0
GAIN0
GAIN1
2323...
LINE 1
1212...
LINE 1
ODD FIELD
GAINX
FRAME N+1
GAIN0
2323...
LINE 2
0101...
LINE 2
GAIN2
GAINX
LINE M–1
LINE M–1
GAIN3
GAIN1
GAIN2
LINE M
LINE M
REV. B

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