AD9895KBCZRL Analog Devices Inc, AD9895KBCZRL Datasheet - Page 40

• Manufacturer Part Number: AD9895KBCZRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9891/AD9895
CIRCUIT LAYOUT INFORMATION
The AD9891/AD9895 Typical Circuit Connection is shown in
Figure 50. Note that Pins E1 and E2 will be No Connects when
using the AD9891. The PCB layout is critical in achieving good
image quality from the AD989x products. All of the supply pins,
particularly the AVDD1, TCVDD, RGVDD, and HVDD sup-
plies, must be decoupled to ground with good quality high
frequency chip capacitors. The decoupling capacitors should be
located as close as possible to the supply pins and should have
a very low impedance path to a continuous ground plane.
There should also be a 4.7 µF or larger value bypass capacitor
for each main supply—AVDD, RGVDD, HVDD, and DRVDD
—although this is not necessary for each individual pin. In most
applications, it is easier to share the supply for RGVDD and
HVDD, which may be done as long as the individual supply
pins are separately bypassed. A separate 3 V supply may also be
used for DRVDD, but this supply pin should still be decoupled
to the same ground plane as the rest of the chip. A separate
ground for DRVSS is not recommended.
The analog bypass pins (BYP1–3, VRB, VRT) should also be
carefully decoupled to ground as close as possible to their re-
spective pins. The analog input (CCDIN) capacitor should also
be located close to the pin.
DATA OUTPUTS
SUPPLY
DRIVER
VSUB TO CCD
3V
+
4.7 F
LINE/FIELD/CLAMP SYNC TO ASIC/DSP
10
0.1 F
EXTERNAL SYNC FROM ASIC/DSP
(MSB) D11
DRVDD
SUBCK
DRVSS
Figure 50. AD9891/AD9895 Typical Circuit Configuration
VSUB
D10
D3
D4
D5
D6
D7
D8
D9
V1
V2
V3
ANALOG
SUPPLY
F1
G2
G1
H2
H1
J2
J1
K2
K1
K3
K4
J3
J4
K5
J5
K6
3V
5
TO V-DRIVER
VSG1–VSG4,
SUBCK
V1–V4,
9
(Not to Scale)
AD9895
TOP VIEW
0.1 F
–40–
The H1–H4 and RG traces should be designed to have low
inductance to avoid excessive distortion of the signals. Heavier
traces are recommended because of the large transient current
demand on H1–H4 by the CCD. If possible, physically locating
the AD9891/AD9895 closer to the CCD will reduce the induc-
tance on these lines. As always, the routing path should be as
direct as possible from the AD9891/AD9895 to the CCD.
The AD9891/AD9895 also contains an on-chip oscillator for
driving an external crystal. Figure 51 shows an example appli-
cation using a typical 18 MHz crystal. For the exact values of
the external resistors and capacitors, it is best to consult with
the crystal manufacturer’s data sheet.
0.1 F
A10
B10
C10
D10
E10
A5
A6
B6
B7
A7
A8
B8
A9
B9
C9
D9
Figure 51. Crystal Driver Application
3
REFT
REFB
AVSS2
AVDD2
BYP3
CCDIN
BYP2
BYP1
AVSS1
AVDD1
TCVDD
TCVSS
CLI
CLO
RGVDD
RG
AD9891/AD9895
TO STROBE CIRCUIT
TO MECHANICAL SHUTTER CIRCUIT
SERIAL INTERFACE TO ASIC OR DSP
20pF
C10
CLI
1 F
1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
18MHz
XTAL
1M
0.1 F
+
+
5
4.7 F
4.7 F
0.1 F
500
CLO
20pF
RG, H1–H4 TO CCD
3V
ANALOG
SUPPLY
OUTPUT FROM CCD
3V
ANALOG
SUPPLY
MASTER CLOCK INPUT
5V
RG
SUPPLY
5V
H1–H4
SUPPLY
+
4.7 F
REV. A