AD9807JS Analog Devices Inc, AD9807JS Datasheet
AD9807JS
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AD9807JS Summary of contents
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FEATURES 12-Bit 6 MSPS A/D Converter Integrated Triple Correlated Double Sampler 3-Channel, 2 MSPS Color Mode 1 – 4 Analog Programmable Gain Amplifier Pin Compatible 10-Bit Version Pixel-Rate Digital Gain Adjustment Pixel-Rate Digital Offset Adjustment Internal Voltage Reference No ...
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AD9807–SPECIFICATIONS ANALOG SPECIFICATIONS Parameter RESOLUTION AD9807 AD9805 CONVERSION RATE 3-Channel Mode With CDS 1 1-Channel Mode With CDS DC ACCURACY 2 Integral Nonlinearity (INL) 2 Differential Nonlinearity (DNL) No Missing Codes AD9807 AD9805 Unipolar Offset Error (@ +25 C) Gain ...
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TIMING SPECIFICATIONS (T Parameter CLOCK PARAMETERS 3-Channel Conversion Rate 1-Channel Conversion Rate CDSCK1 Pulse Width CDSCK1 Pulse Width CDSCK2 Pulse Width CDSCK2 Pulse Width CDS Clocks Digital Quiet Time CDSCK2 Falling to CDSCK1 Rising CDSCK2 Falling to CDSCK1 Rising CDSCK1 ...
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AD9807 AVDD AVSS CAPT CAPT CAPB CAPB VREF AVSS VING AVSS AVSS AVDD STRTLN Pin No. Pin Name 1, 15 AVDD 2, 10, 12, 14 AVSS 3, 4 CAPT 5, 6 CAPB 7 VREF 8 CML 9 VINR 11 VING ...
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AVDD AVSS CAPT CAPT CAPB CAPB VREF AVSS AVSS AVSS AVDD STRTLN CONNECT Pin No. Pin Name 1, 15 AVDD 2, 10, 12, 14 AVSS 3, 4 CAPT 5, 6 CAPB 7 VREF 8 CML 9 VINR ...
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AD9807 ABSOLUTE MAXIMUM RATINGS* With Respect Parameter to Min Max AVDD AVSS –0.5 AVSS AVSS –6.5 DVDD DVSS –0.5 AGND DVSS –1.0 AVDD DVDD –6.5 Clock Input DVSS –0.5 Digital Ouputs DVSS –0.5 AIN, VREF AVSS –0.3 Junction Temperature Storage ...
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ANALOG INPUTS t AD STRTLN t C1C2A t C1A CDSCLK1 t C1AD CDSCLK2 t ACLK ADCCLK R GAIN<n:0> OFFSET<m:0> ANALOG INPUTS (0V) STRTLN CDSCLK1 t ACLK ADCCLK GAIN<n:0> OFFSET<m:0> ANALOG t INPUTS AD STRTLN t C1B t C1C2B ...
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AD9807 ANALOG INPUTS (0V) STRTLN CDSCLK1 ADCCLK GAIN<n:0> OFFSET<m:0> Figure 1d. 1-Channel SHA-Mode Clock Timing (All Channels) ANALOG INPUTS STRTLN CDSCLK1 t Q CDSCLK2 ADCCLK GAIN<n:0> OFFSET<m:0> OEB CSB A0, A1, A2 WRB MPU<7:0> ...
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CSB A0, A1, A2 RDB MPU<7:0> RED VINR CDS PGA GREEN VING CDS PGA BLUE VINB CDS PGA CDSCLK1 CDSCLK2 STRTLN ADCCLK REGISTER OVERVIEW MPU Port Map Table II shows the MPU Port Map; the MPU Port ...
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AD9807 FULL SCALE 4X FULL SCALE 2X FULL SCALE 10-BIT GAIN, 10-BIT OFFSET 11-BIT GAIN, 9-BIT OFFSET 12-BIT GAIN, 8-BIT OFFSET COLOR0 COLOR1 Figure 5. AD9807 Configuration Register Format Configuration Register/AD9805 ...
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The offset is variable in 256 steps. The contents of the color pointer in the Configuration Register at the time an ADC Offset Register is written indicates the color for which that ...
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AD9807 FUNCTIONAL OVERVIEW It is possible to operate the AD9807 in one of five modes: 3-Channel Operation with CDS, 3-Channel SHA Operation, 1-Channel Operation with CDS, 1-Channel SHA Operation; and 2-Channel Bayer Mode. A description of each of the five ...
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SHA Operation This mode of the AD9807 enables single-channel, or mono- chrome sampling; it differs from the CDS monochrome sampling mode in that the CDS function is replaced with a simple sample-and-hold amplifier (SHA). CDSCLK1 becomes the sample-and-hold clock; ...
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AD9807 PIXEL n RIN, GIN, BIN CDSCLK1 CDSCLK2 ADCCLK R DATA<11:0> GAIN<n:0> R (n) G (n) GAIN<m:0> PIXEL n RIN, GIN, BIN CDSCLK1 ADCCLK R DATA<11:0> GAIN<n:0> R (n) G (n) GAIN<m:0> PIXEL n RIN, GIN, BIN CDSCLK1 CDSCLK2 ADCCLK ...
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PIXEL n RIN, GIN, BIN CDSCLK1 ADCCLK DATA<11:0> GAIN<n:0> G (n) OFFSET<m:0> 4.0 3.5 3.0 2.5 GAIN (dB) 2.0 1.5 1 PGA GAIN SETTING Figure 16. PGA ...
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AD9807 Choosing the Input Coupling Capacitors Because of the dc offset present at the output of CCDs likely that these outputs will require some form of dc-restora- tion to be compatible with the input requirements of the AD9807. ...
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Note that a capacitor larger than 133 pF would still work, it would just take several lines to charge the input capacitor up to the full V level. Another option to lengthen T C clocking the CCD and CDSCLK1 while ...
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AD9807 To calibrate the AD9807 for a particular scan, use the following sequence. SET PGA GAIN(S) (INPUT OFFSET = 0mV) SCAN DARK LINE COMPUTE PIXEL OFFSETS SET INPUT OFFSET SET ODD/EVEN OFFSET SET YES ANOTHER COLOR ? NO SET GAIN/OFFSET ...
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CIS Application Unlike many other integrated circuit CCD signal processors, the AD9807 can easily be implemented in imaging systems that do not use a CCD. By disabling the input clamp and the CDS blocks, any dc coupled signal within the ...
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AD9807 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 64-Terminal PQFP (S-64) 0.687 (17.45) 0.667 (16.95) 0.093 (2.35) 0.555 (14.10) MAX 0.547 (13.90) 0.472 (12.0) BSC 0.041 (1.03) 0.029 (0.73 PIN 1 SEATING PLANE TOP VIEW ...