AD9807JS Analog Devices Inc, AD9807JS Datasheet - Page 13

• Manufacturer Part Number: AD9807JS
• Description: IC CCD SIGNAL PROC 12BIT 64-PQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9807JS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: Microprocessor
• Current - Supply: 86mA
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

1-Channel SHA Operation
This mode of the AD9807 enables single-channel, or mono-
chrome sampling; it differs from the CDS monochrome
sampling mode in that the CDS function is replaced with a
simple sample-and-hold amplifier (SHA). CDSCLK1 becomes
the sample-and-hold clock; CDSCLK2 is tied to ground. The
input is sampled on the falling edge of CDSCLK1. The input
waveform would typically be either dc coupled and level shifted,
or dc restored prior to driving either the VINR, VING, and
VINB pins of the AD9807 (clamp mode should not be enabled).
Bits 6 and 7 in the Configuration Register select the desired
input. The input signal in this mode is ground referenced. The
input signal is not inverted prior to amplification by the PGA;
the setting in the corresponding PGA Gain Register determines
the gain of the PGA. The offset of the input signal is modified
by the value stored in the ADC offset register. This signal is
then routed through a high speed multiplexer to a 12-bit A/D
converter (10-bit for AD9805) for digitization; the multiplexer
does not cycle in this mode. After digitization, the data is
modified by the amount indicated in the Odd and Even Offset
Registers. A digital subtracter allows additional pixel rate offset
modification of the signal based on the values written to the
OFFSET data bus. Finally, a digital multiplier allows pixel rate
gain modification of the signal based on the values written to the
GAIN data bus. Latency is 6 ADCCLK cycles (7 cycles for
gain and offset; see Figure 15).
The state of STRTLN is evaluated on the rising edges of
ADCCLK. When STRTLN is low, the internal circuitry is
reset on the next rising edge of ADCCLK; the odd/even
circuitry is configured to expect even pixels. After STRTLN
goes high, the first set of pixels are assumed to be even. Con-
secutive pixels (red, green, or blue) are assumed to alternate
between odd and even pixel sets. The blue and green channels
are recommended for single channel operation; if using red,
invert ADCCLK in Figure 1d.
2-Channel Bayer Mode Operation with CDS
This mode of the AD9807 enables single-channel, or mono-
chrome, sampling; The CCD waveform is ac coupled to both
the VING and VINB pins of the AD9807 where it is biased at
an appropriate voltage level using the on-chip clamp; the input
may alternatively be dc coupled if it has already been appropri-
REV. 0
DATA<11:0>
ADCCLK
OEB
t
OD
Figure 11. Digital Output Timing
–13–
ately level shifted. The internal CDS takes two samples of the
incoming pixel data: the first sample (CDSCLK1) is taken
during the reset time while the second sample (CDSCLK2) is
taken during the video, or data, portion of the input pixel. The
offset of the input signal is modified by the value stored in the
ADC offset register. The voltage difference of the reset level
and video level is inverted and amplified by the PGA; the setting
in the corresponding PGA Gain Register determines the gain of
the PGA. The output from the PGA is then routed through a
high speed multiplexer to a 12-bit A/D converter (10-bit for
AD9805) for digitization; the multiplexer does cycle in this
mode. After digitization, the data is modified by the amount
indicated in the Even Offset Registers. A digital subtracter
allows additional pixel rate offset modification of the signal
based on the values written to the OFFSET data bus. Finally, a
digital multiplier allows pixel rate gain modification of the signal
based on the values written to the GAIN data bus. Latency is
6 ADCCLK cycles (7 cycles for the gain and offset bus; see
Figure 14).
The state of STRTLN is evaluated on the rising edges of
ADCCLK. When STRTLN is low, the internal circuitry is
reset on the next rising edge of ADCCLK; the odd/even
circuitry is configured to expect even pixels.
This feature has been included to accommodate the use of the
part with an area CCD (Bayer mode). The mode is initiated by
writing a one to the LSB of the register at Address 7. The write
to enable the mode, should be performed when the STRTLN
input is inactive (low) and the ADCCLK is running. The first
pixel after an active edge on STRTLN will be a green pixel. All
pixels in Bayer Mode are even and use the even offset registers.
The line will continue alternating GRGRGR pixels until
STRTLN goes inactive. The next line will be BGBGBG pixels
(the first pixel after the active STRTLN edge being blue). Line
type will then alternate between GRGRGR and BGBGBG type.
To reset the next line to GRGRGR type at the start of the next
frame/image, rewrite the Bayer mode enable bit to a one during
the inactive STRTLN period. All red and blue pixels pass
through the blue channel of the part and use the blue PGA and
offset registers. To use a different offset/PGA gain value the
register must be written to between lines. Green pixels on either
line type pass through the green channel.
t
HZ
t
EDV
AD9807