AD9826KRS Analog Devices Inc, AD9826KRS Datasheet - Page 3

• Manufacturer Part Number: AD9826KRS
• Description: IC IMAGE SGNL PROC 16BIT 28-SSOP
• Manufacturer: Analog Devices Inc
• Type: Image Sensorr

Specifications of AD9826KRS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 75mA
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Input Voltage Range: 2V
• Operating Supply Voltage (min): 3/4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Resolution: 16b
• Supply Current: 5/75mA
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Number Of Channels: 3
• Lead Free Status / RoHS Status: Not Compliant

DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
LOGIC OUTPUTS
LOGIC OUTPUTS (with DRVDD = 3 V)
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
CLOCK PARAMETERS
SERIAL INTERFACE
DATA OUTPUTS
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
High Level Output Voltage, (I
Low Level Output Voltage (I
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
Maximum SCLK Frequency
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Set-Up Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
OL
OH
= 50 A)
= 50 A)
(T
(T
C
MIN
L
MIN
= 10 pF, unless otherwise noted.)
to T
to T
MAX
MAX
, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
Symbol
V
V
I
I
C
V
V
I
I
V
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
SCLK
IH
IL
OH
OL
PRA
PRB
ADCLK
C1
C2
C1C2
ADC2
C2ADR
C2ADF
C2C1
AD
LS
LH
DS
DH
RDV
OD
DV
HZ
IH
IL
OH
OL
OH
OL
IN
Min
2.0
4.5
2.95
Min
200
80
30
8
8
0
0
5
30
5
10
10
10
10
10
10
ADCCLK
= 15 MHz, f
Typ
10
10
10
50
50
Typ
2
6
10
10
3 (Fixed)
CDSCLK1
= f
Max
0.8
0.1
0.05
Max
CDSCLK2
= 5 MHz,
AD9826
Unit
V
V
pF
V
V
V
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
A
A
A
A