AD9943KCP Analog Devices Inc, AD9943KCP Datasheet - Page 15

• Manufacturer Part Number: AD9943KCP
• Description: IC CCD SIGNAL PROCESSOR 32-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9943KCP

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: LFCSP EP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT DESCRIPTION AND OPERATION
The AD9943/AD9944 signal processing chain is shown in
Figure 12. Each processing step is essential for achieving a high
quality image from the raw CCD pixel data.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, which is compatible with the 3 V single
supply of the AD9943/AD9944.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract video
information and reject low frequency noise. The timing shown
in Figure 14 illustrates how the two CDS clocks, SHP and SHD,
are used, respectively, to sample the reference level and data
level of the CCD signal. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical for achieving the best performance from the
CCD. An internal SHP/SHD delay (t
internal propagation delays.
0.1µF
CCDIN
ID
) of 3 ns is caused by
DC RESTORE
CDS
Figure 12. CCD Mode Block Diagram
Rev. B | Page 15 of 20
REGISTER
VGA GAIN
VGA
6dB TO 40dB
10
OPTICAL BLACK CLAMP
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with the
fixed black level reference selected by the user in the clamp level
register. The resulting error signal is filtered to reduce noise, and
the correction value is applied to the ADC input through a D/A
converter. Normally, the optical black clamp loop is turned on
once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital
clamping is used during the post processing, the optical black
clamping for the AD9943/AD9944 may be disabled using
Bit D3 in the operation register. Refer to Table 9 and Figure 10
and Figure 11.
When the loop is disabled, the clamp level register may still be
used to provide programmable offset adjustment. Horizontal
timing is shown in Figure 15. The CLPOB pulse should be
placed during the CCD’s optical black pixels. It is recommended
that the CLPOB pulse be used during valid CCD dark pixels.
The CLPOB pulse should be a minimum of 20 pixels wide to
minimize clamp noise. Shorter pulse widths may be used, but
clamp noise may increase and the loop’s ability to track low
frequency variations in the black level is reduced.
8-BIT
DAC
FILTERING
DIGITAL
OPTICAL BLACK
INTERNAL
10-/12-BIT
CLAMP
V
ADC
REF
2V FULL SCALE
CLAMP LEVEL
REGISTER
8
10/12
AD9943/AD9944
DOUT
CLPOB