DS92LV1021TMSA/NOPB National Semiconductor, DS92LV1021TMSA/NOPB Datasheet - Page 16

• Manufacturer Part Number: DS92LV1021TMSA/NOPB
• Description: IC SERIALIZER 10-BIT 28-SSOP
• Manufacturer: National Semiconductor

Specifications of DS92LV1021TMSA/NOPB

• Function: Serializer
• Data Rate: 400Mbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVDS
• Number Of Inputs: 10
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Serdes Function: Serializer
• Ic Output Type: LVDS
• No. Of Inputs: 10
• No. Of Outputs: 1
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: SSOP
• No. Of Pins: 28
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 400Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV1021TMSA; *DS92LV1021TMSA/NOPB; DS92LV1021TMSA

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ROUT
RCLK_R/F
RI+
RI−
PWRDN
LOCK
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
Deserializer Pin Description
Pin Name
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
15–19, 24–28
14, 20, 22
1, 12, 13
21, 23
4, 11
No.
10
2
5
6
7
9
8
3
Data Output.
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wire OR connection.
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9,
LOCK and RCLK when driven low.
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
16
±
9 mA CMOS level outputs.
Description