DS92LV1021TMSA/NOPB National Semiconductor, DS92LV1021TMSA/NOPB Datasheet - Page 6

• Manufacturer Part Number: DS92LV1021TMSA/NOPB
• Description: IC SERIALIZER 10-BIT 28-SSOP
• Manufacturer: National Semiconductor

Specifications of DS92LV1021TMSA/NOPB

• Function: Serializer
• Data Rate: 400Mbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVDS
• Number Of Inputs: 10
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Serdes Function: Serializer
• Ic Output Type: LVDS
• No. Of Inputs: 10
• No. Of Outputs: 1
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: SSOP
• No. Of Pins: 28
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 400Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV1021TMSA; *DS92LV1021TMSA/NOPB; DS92LV1021TMSA

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t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
RFCP
RFDC
RFCP
TCP
RFTT
RCP
CLH
CHL
DD
ROS
ROH
RDC
HZR
LZR
ZHR
ZLR
DSR1
DSR2
ZHLK
RNM
Symbol
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time
required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change
from not receiving data to receiving synchronization patterns (SYNCPATs).
Note 6: tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
/
Receiver out Clock
Period
CMOS/TTL Low-to-High
Transition Time
CMOS/TTL High-to-Low
Transition Time
Deserializer Delay
ROUT (0-9) Setup Data
to RCLK
ROUT (0-9) Hold Data
to RCLK
RCLK Duty Cycle
HIGH to TRI-STATE
Delay
LOW to TRI-STATE
Delay
TRI-STATE to HIGH
Delay
TRI-STATE to LOW
Delay
Deserializer PLL Lock
Time from PWRDWN
(with SYNCPAT)
Deserializer PLL Lock
time from SYNCPAT
TRI-STATE to HIGH
Delay (power-up)
Deserializer Noise
Margin
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK Periods
REFCLK Transition Time
Parameter
Parameter
CC
= 3.3V and T
Figure 9
t
CL = 15 pF
Figure 4
Figure 10
Figure 11
Figure 12
(Note 5)
Figure 13
Figure 14
Figure 15
(Note 6)
RCP
= t
Conditions
TCP
A
Conditions
= +25˚C.
Rout(0-9),
Rout(0-9),
Pin/Freq.
16MHz
40MHz
16MHz
40MHz
16 MHz
40 MHz
LOCK,
LOCK
LOCK
RCLK
RCLK
RCLK
6
0.83
Min
−0.4*t
25
1.75*t
0.4*t
Min
RCP
400
100
25
40
RCP
RCP
4.2+0.5*t
6.5+0.5*t
1.75*t
Typ
4+0.5*t
6+0.5*t
50
−0.5*t
T
1
3
0.5*t
1100
Typ
400
4.8
4.5
1.5
50
2
2
7
7
RCP
RCP
RCP
RCP
RCP
RCP
RCP
+3
1.75*t
10+t
10+t
12+t
12+t
Max
62.5
1.03
Max
62.5
25.6
6
60
15
10
12
5
5
7
RCP
RCP
RCP
RCP
RCP
+7
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ps
ps
ns
ns
%
%