LM2502SQX/NOPB National Semiconductor, LM2502SQX/NOPB Datasheet - Page 7
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LM2502SQX/NOPB
Manufacturer Part Number
LM2502SQX/NOPB
Description
IC SER/DESER MPL DISPL 40-LLP
Manufacturer
National Semiconductor
Series
LMr
Datasheet
1.LM2502SMNOPB.pdf
(27 pages)
Specifications of LM2502SQX/NOPB
Function
Serializer/Deserializer
Data Rate
307Mbps
Input Type
LVCMOS
Output Type
LVCMOS
Number Of Inputs
22
Number Of Outputs
3
Voltage - Supply
1.7 V ~ 3.3 V
Operating Temperature
-30°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-LLP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM2502SQX
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LM2502SQX/NOPB
Manufacturer:
NS
Quantity:
2 000
SUPPLY CURRENT
I
I
PARALLEL BUS TIMING
t
t
t
t
CLK
Parallel Bus Timing - See Figures 13, 14, 15, 16 and
Table 5, Table 6, Table 7, and Table 8
SERIAL BUS TIMING
t
t
POWER UP TIMING(Note 5)
t
t
t
t
t
t
DD
DDZ
SET
HOLD
RISE
FALL
DVBC
DVAC
0
1
2
3
4
5
Symbol
Symbol
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
DC
Total Supply
Current — Enabled
Conditions: MC = 76.8
MHz, MD = 1010-0101
pattern (worse case toggle,
rail-to-rail levels), CLK =
19.2 MHz (4X) (Note 7)
Total Supply
Current — Enabled
Conditions: MC = 20 MHz,
MD = 1010-0101 pattern
(worse case toggle,
rail-to-rail levels), CLK = 5
MHz (4X)
Supply Current — Disabled
Set Up Time, Data to Edge
Hold Time, Edge to Data
Rise Time
Fall Time
Output Clock Duty Cycle
Data Valid before Clock
Data Valid after Clock
Master PLL Lock Counter
MC Pulse Width Low
(Master)
MC Pulse Width HIGH
(Master)
MC Pulse Width Low
(Master)
CLK-Out Delay (Slave)
Power Up Total delay
(t
0
+ t
1
+ t
Parameter
Parameter
2
+ t
3
+ t
4
)
Master
Slave, C
Master
Slave, C
Power_Down Mode, PD* = 0V
Inputs
Figure 2, Outputs,
C
Edge sensitive
outputs tested
only:
m68 mode: CS1
CS2
i80 mode: RD
WR
CLKDIS
Master-to-Slave
(Note 5)
L
= 10 pF
(Continued)
*
*
, and CLKout
and CLKout
*
L
L
= 10 pF
= 10 pF
= H, Slave (DES)
Conditions
*
Conditions
,
*
,
V
V
V
V
Figure 6
V
V
V
V
V
V
V
V
DDIO
DDIO
DDIO
DDIO
7
DDIO
DD
DDIO
DD
DDIO
DD
DDIO
DD
= V
= V
= V
= V
= 1.7V
= 3.3V
= 1.7V
= 3.3V
= 1.8V
= 1.8V
DDA
DDA
DDA
DDA
= 3V
= 3V
Min
2.0
0.5
Min
5
5
2
1
2
1
4096
4133
Typ
Typ
50
11
11
11
1.5
9.0
15
14
10
7
2
6
2
7
5
1
4
1
Max
Max
13.0
220
14
10
14
10
9.0
25
10
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cycles
cycles
cycles
cycles
cycles
cycles
Units
Units
CLK
CLK
CLK
CLK
CLK
MC
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns
ns
ns
ns
ns
µA
µA
µA
%