ISL34341INZ Intersil, ISL34341INZ Datasheet - Page 5

• Manufacturer Part Number: ISL34341INZ
• Description: IC VIDEO SERDES LONG 64-EPTQFP
• Manufacturer: Intersil

Specifications of ISL34341INZ

• Function: Serializer/Deserializer
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 2
• Number Of Outputs: 2
• Voltage - Supply: 1.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -

Electrical Specifications
Pin Descriptions
HS Generated Output Common Mode Voltage
HS Common Mode Serializer-Deserializer
Voltage Difference
HS Differential Output Impedance
HS Output Latency
HS Output Rise and Fall Times
HS Differential Skew
HS Output Random Jitter
HS Output Deterministic Jitter
HIGH SPEED RECEIVER
HS Differential Input Voltage
HS Generated Input Common Mode Voltage
HS Differential Input Impedance
HS Maximum Jitter Tolerance
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
C
C Clock Rate (on SCL)
C Clock Pulse Width (HI or LO)
C Clock Low to Data Out Valid
C Start/Stop Setup/Hold Time
C Data in Setup Time
C Data in Hold Time
C Data out Hold Time
PIN NUMBER
52 to 63,
2 to 13
41, 40
22
23
21
26
51
24
25
PARAMETER
RGBA[7:0],
RGBB[7:0], RGBC[7:0]
HSYNC
VSYNC
DATAEN
PCLK_IN
PCLK_OUT
SERIOP, SERION
HSYNCPOL
VSYNCPOL
PIN NAME
5
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V
VDD_TX = VDD_P = VDD_AN = 3.3V, T
capacitor = 27nF. (Continued)
Parallel video data LVCMOS inputs
Horizontal (line) Sync LVCMOS input
Vertical (frame) Sync LVCMOS input
Video Data Enable LVCMOS input
Pixel clock LVCMOS input
Default; not used
High speed differential serial I/O
CMOS input for HSYNC
1: HSYNC is active low
0: HSYNC is active high
CMOS input for VSYNC
1: VSYNC is active low
0: VSYNC is active high
SYMBOL
t
V
ΔV
R
SKEW
V
t
t
V
R
f
OCM
LPD
R/
t
t
OUT
I2C
ICM
RJ
DJ
ID
CM
IN
t
F
Part-to-part
20% to 80%
SERIALIZER
ISL34341
CONDITIONS
A
= +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling
DESCRIPTION
Parallel video data LVCMOS outputs
Horizontal (line) Sync LVCMOS output
PLL reference clock LVCMOS input
Recovered clock LVCMOS output
Vertical (frame) Sync LVCMOS output
Video Data Enable LVCMOS output
High speed differential serial I/O
MIN
150
100
100
100
1.3
0.6
80
80
4
0
TYP
2.35
13.4
2.32
0.52
100
150
<10
100
100
20
40
DESERIALIZER
7
,
MAX
120
120
120
400
10
1
October 8, 2010
UNITS
mV
PCLK
ps
ps
UI
FN6827.1
kHz
mV
ms
µs
µs
µs
ns
ns
ps
ps
Ω
Ω
V
V
P-P
rms
P-P
P-P