DS90LV804TSQX/NOPB National Semiconductor, DS90LV804TSQX/NOPB Datasheet - Page 5

• Manufacturer Part Number: DS90LV804TSQX/NOPB
• Description: IC BUFFER/REPEATR LVDS 4CH 32LLP
• Manufacturer: National Semiconductor
• Type: Bufferr

Specifications of DS90LV804TSQX/NOPB

• Tx/rx Type: LVDS
• Delay Time: 3.2ns
• Capacitance - Input: 3.5pF
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 140mA
• Mounting Type: Surface Mount
• Package / Case: 32-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90LV804TSQX

LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V
ΔV
V
ΔV
I
C
SUPPLY CURRENT (Static)
I
I
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
t
t
t
t
t
t
t
t
t
OS
CC
CCZ
LHT
HLT
PLHD
PHLD
SKD1
SKCC
SKP
JIT
ON
OFF
Symbol
OD
OS
OUT2
Note 5: Typical parameters are measured at V
Note 6: Differential output voltage V
Note 7: Output offset voltage V
Note 8: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 9: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V
MHz, t
Note 10: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V
Mbps, t
Note 11: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input
voltage = V
Note 12: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
OD
OS
r
r
= t
= t
f
Differential Output Voltage (Note
6)
Change in V
Complementary States
Offset Voltage (Note 7)
Change in V
Complementary States
Output Short Circuit Current
Output Capacitance
Total Supply Current
TRI-STATE Supply Current
Differential Low to High
Transition Time
Differential High to Low
Transition Time
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Pulse Skew
Output Channel to Channel Skew Difference in propagation delay (t
Part to Part Skew
Jitter
(Note 8)
LVDS Output Enable Time
LVDS Output Disable Time
f
= 50ps (20% to 80%).
ID
= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
= 500mV, 2
Parameter
23
OD
OS
-1 PRBS pattern at 800 Mbps, t
between
between
OS
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
OD
is defined as ABS(OUT+–OUT−). Differential input voltage V
DD
= 3.3V, T
R
OUT−
OUT+ or OUT− Short to GND
OUT+ or OUT− to GND when TRI-STATE
All inputs and outputs enabled and active,
terminated with external differential load of 100Ω
between OUT+ and OUT-.
EN = 0V
Use an alternating 1 and 0 pattern at 200 Mbps,
measure between 20% and 80% of V
12)
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% V
|t
among all output channels. (Note 12)
Common edge, parts at same temp and V
12)
RJ - Alternating 1 and 0 at 400 MHz (Note 9)
DJ - K28.5 Pattern, 800 Mbps (Note 10)
TJ - PRBS 2
Time from EN to OUT± change from TRI-STATE to
active.
Time from EN to OUT± change from active to TRI-
STATE.
PLHD
L
= 100Ω external resistor between OUT+ and
r
A
= t
–t
= 25°C. They are for reference purposes, and are not production-tested.
PHLD
f
= 50ps (20% to 80%).
| (Note 12)
23
-1 Pattern, 800 Mbps (Note 11)
OD
Conditions
5
between input to output.
PLHD
OD
ID
or t
is defined as ABS(IN+–IN−).
. (Note
PHLD
CC
(Note
)
1.05
Min
250
−35
−35
ID
ID
= 500mV, K28.5 pattern at 800
= 500mV, 50% duty cycle at 400
(Note 5)
1.18
Typ
500
−60
117
210
210
5.5
2.7
2.0
2.0
1.1
25
50
15
30
1.475
Max
600
−90
140
300
300
125
300
3.2
3.2
1.1
1.5
35
35
80
35
55
12
6
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psrms
Units
psp-p
psp-p
mV
mV
mV
mA
mA
mA
pF
ps
ps
ns
ns
ps
ps
ns
ns
ns
V