PCA9545AD,118 NXP Semiconductors, PCA9545AD,118 Datasheet - Page 17

• Manufacturer Part Number: PCA9545AD,118
• Description: IC I2C SWITCH 4CH 20-SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9545AD,118

• Applications: 4-Channel I²C Switcher
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Package / Case: 20-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• Logical Function: I2C Multiplexer
• Configuration: 1 x 4:1
• Number Of Inputs: 4
• Number Of Outputs: 1
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Power Dissipation: 400mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1864-2; 935275808118; PCA9545AD-T

NXP Semiconductors
11. Dynamic characteristics
Table 9.
[1]
[2]
[3]
[4]
[5]
PCA9545A_45B_45C_7
Product data sheet
Symbol
t
f
t
t
t
t
t
t
t
t
t
t
C
t
t
t
INT
t
t
t
t
RESET
t
t
t
PD
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
SU;STO
HD;DAT
SU;DAT
r
f
SP
VD;DAT
VD;ACK
v(INTnN-INTN)
d(INTnN-INTN)
w(rej)L
w(rej)H
w(rst)L
rst
REC;STA
b
Pass gate propagation delay is calculated from the 20
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
bridge the undefined region of the falling edge of SCL.
C
Measurements taken with 1 k pull-up resistor and 50 pF load.
b
= total capacitance of one bus line in pF.
Dynamic characteristics
Parameter
propagation delay
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data set-up time
rise time of both SDA and SCL
signals
fall time of both SDA and SCL signals
capacitive load for each bus line
pulse width of spikes that must be
suppressed by the input filter
data valid time
data valid acknowledge time
valid time from INTn to INT signal
delay time from INTn to INT inactive
LOW-level rejection time
HIGH-level rejection time
LOW-level reset time
reset time
recovery time to START condition
Rev. 07 — 19 June 2009
Conditions
from SDA to SDx,
or SCL to SCx
HIGH-to-LOW
LOW-to-HIGH
INTn inputs
INTn inputs
SDA clear
typical R
4-channel I
on
and the 15 pF load capacitance.
2
C-bus switch with interrupt logic and reset
[2]
[5]
[5]
PCA9545A/45B/45C
Standard-mode
Min
250
500
4.7
4.0
4.7
4.0
4.7
4.0
0
0.5
0
1
4
0
-
-
-
-
-
-
-
-
-
-
[3]
I
2
C-bus
0.3
1000
Max
3.45
100
300
400
0.6
50
1
1
4
2
-
-
-
-
-
-
-
-
-
-
-
-
[1]
IH(min)
20 + 0.1C
20 + 0.1C
Fast-mode I
of the SCL signal) in order to
Min
100
500
1.3
0.6
1.3
0.6
0.6
0.6
0
0.5
0
1
4
0
-
-
-
-
-
-
-
-
[3]
© NXP B.V. 2009. All rights reserved.
b
b
[4]
[4]
2
C-bus Unit
0.3
Max
400
300
300
400
0.9
0.6
50
1
1
4
2
-
-
-
-
-
-
-
-
-
-
-
-
[1]
17 of 28
ns
kHz
ns
ns
ns
pF
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
s