PCA9541APW/03,112 NXP Semiconductors, PCA9541APW/03,112 Datasheet - Page 30

• Manufacturer Part Number: PCA9541APW/03,112
• Description: IC I2C 2:1 SELECTOR 16-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9541APW/03,112

• Package / Case: 16-TSSOP
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Frequency: 400 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4937-5; 935289366112

NXP Semiconductors
13. Dynamic characteristics
Table 17.
[1]
[2]
[3]
PCA9541A_3
Product data sheet
Symbol
t
f
f
t
t
t
t
t
t
t
t
t
t
C
t
t
t
INT
t
t
t
t
RESET
t
t
t
PD
SCL
SCL(init/rec)
BUF
HD;STA
LOW
HIGH
SU;STA
SU;STO
HD;DAT
SU;DAT
r
f
SP
VD;DAT
VD;ACK
v(INT_IN-INTn)
d(INT_IN-INTn)
w(rej)L
w(rej)H
w(rst)L
rst
REC;STA
b
Pass gate propagation delay is calculated from the 20
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
bridge the undefined region of the falling edge of SCL.
Dynamic characteristics
Parameter
propagation delay
SCL clock frequency
SCL clock frequency
(bus initialization/bus recovery)
bus free time between a STOP and
START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data set-up time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
pulse width of spikes that must be
suppressed by the input filter
data valid time
data valid acknowledge time
valid time from pin INT_IN to pin INTn
signal
delay time from pin INT_IN to pin INTn
inactive
LOW-level rejection time
HIGH-level rejection time
LOW-level reset time
reset time
recovery time to START condition
Rev. 03 — 16 July 2009
2-to-1 I
Conditions
(SDA_MSTn to
SDA_SLAVE) or
(SCL_MSTn to
SCL_SLAVE)
HIGH-to-LOW
LOW-to-HIGH
INT_IN input
INT_IN input
SDA clear
typical R
2
on
C-bus master selector with interrupt logic and reset
and the 15 pF load capacitance.
[6][7]
[1]
[2]
[5]
[5]
Standard-mode
Min
250
500
4.7
4.0
4.7
4.0
4.7
4.0
0
0.5
50
10
0
1
0
-
-
-
-
-
-
-
-
-
-
[3]
I
2
C-bus
1000
Max
3.45
100
150
300
400
0.3
0.6
50
1
1
4
2
-
-
-
-
-
-
-
-
-
-
-
-
IH(min)
Fast-mode I
20 + 0.1C
20 + 0.1C
of the SCL signal) in order to
PCA9541A
Min
100
500
1.3
0.6
1.3
0.6
0.6
0.6
0
0.5
50
10
0
1
0
-
-
-
-
-
-
-
-
[3]
© NXP B.V. 2009. All rights reserved.
b
b
[4]
[4]
2
C-bus Unit
Max
400
150
300
300
400
0.3
0.9
0.6
50
1
1
4
2
-
-
-
-
-
-
-
-
-
-
-
-
30 of 41
ns
kHz
kHz
ns
ns
ns
pF
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
s