PCA9518APW,512 NXP Semiconductors, PCA9518APW,512 Datasheet - Page 13

• Manufacturer Part Number: PCA9518APW,512
• Description: IC I2C HUB 5CH EXPANDBL 20-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9518APW,512

• Applications: CMOS Bus Controller
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4245-5; 935284254512; PCA9518APW

NXP Semiconductors
10. Dynamic characteristics
Table 6.
V
[1]
[2]
[3]
[4]
PCA9518A_3
Product data sheet
Symbol
t
t
t
t
t
t
t
t
t
PHL
PLH
PHL1
PLH1
PLH2
THL
TLH
su
h
DD
= 3.0 V to 3.6 V
For operation between published voltage ranges, refer to worst-case parameter in both ranges.
The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are
only sensitive to load capacitance. The rise times are RC time constant controlled and therefor a specific numerical value can only be
given for fixed RC time constants.
The SDA HIGH to LOW propagation delay includes the fall time from V
SCL fall time from the quiescent HIGH (usually V
included which make the fall time almost independent of load capacitance.
The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5V
or EXPSCL2, the rise time constant for the quiescent LOW to 0.5V
the quiescent external driven LOW to 0.7V
external resistance and total capacitance for the various nodes.
Parameter
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW propagation delay 1
LOW to HIGH propagation delay 1
LOW to HIGH propagation delay 2
HIGH to LOW output transition time
LOW to HIGH output transition time
set-up time
hold time
Dynamic characteristics
[1]
; V
SS
= 0 V; T
amb
= 40 C to +85 C; unless otherwise specified.
DD
for the SDA or SCL output. All of these rise times are RC time constants determined by the
DD
Rev. 03 — 3 December 2008
) to below 0.3V
Conditions
SDA to SDAn, or
SCL to SCLn;
SDA to SDAn, or
SCL to SCLn;
EXPSDA1 to SDA, or
EXPSCL1 to SCL;
EXPSDA1 to SDA, or
EXPSCL1 to SCL;
EXPSDA2 to SDA, or
EXPSCL2 to SCL;
SDA, SCL;
SDA, SCL;
enable to START condition
enable after STOP condition
Figure 7
Figure 7
DD
DD
. The SDA and SCL outputs have edge rate control circuits
Figure 7
Figure 7
for the EXPSDA1 or EXPSCL1, and the rise time constant from
DD
to 0.5V
Figure 7
Figure 7
Figure 7
DD
of the EXPSDA1 or EXPSCL1 pins and the SDA or
Expandable 5-channel I
[2][3]
[2][4]
Min
105
110
109
130
160
58
-
300
300
Typ
202
259
193
153
234
110
0.85 RC
-
-
PCA9518A
© NXP B.V. 2008. All rights reserved.
DD
for the EXPSDA1
Max
389
265
327
179
279
187
-
-
-
2
C-bus hub
13 of 23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns