LA-ISPPAC-POWR1014-01TN48E Lattice, LA-ISPPAC-POWR1014-01TN48E Datasheet - Page 35

• Manufacturer Part Number: LA-ISPPAC-POWR1014-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of LA-ISPPAC-POWR1014-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• No. Of Macrocells: 24
• Termination Type: SMD
• Supply Voltage Min: 2.8V
• Rohs Compliant: Yes
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Filter Terminals: SMD
• Frequency: 25MHz
• Input Voltage Primary Max: 4.5V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 29 shows how
the instruction and various data registers are organized in an LA-ispPAC-POWR1014/A.
Figure 29. LA-ispPAC-POWR1014/A TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 30. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
TDI
TEST ACCESS PORT (TAP)
CFG ADDRESS REGISTER (12 BITS)
INSTRUCTION REGISTER (8 BITS)
ADDRESS REGISTER (109 BITS)
CFG DATA REGISTER (56 BITS)
TCK
IDCODE REGISTER (32 BITS)
DATA REGISTER (123 BITS)
BYPASS REGISTER (1 BIT)
UES REGISTER (32 BITS)
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
LOGIC
TMS
35
OUTPUT
LATCH
TDO
NON-VOLATILE
MEMORY
E
2
CMOS