PCA9561D,118 NXP Semiconductors, PCA9561D,118 Datasheet - Page 8

• Manufacturer Part Number: PCA9561D,118
• Description: IC I2C EEPROM DIP SWITCH 20SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9561D,118

• Applications: Network, Telecom
• Interface: I²C, SMBus
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 20-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271716118; PCA9561D-T; PCA9561D-T

Philips Semiconductors
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
2004 May 17
Quad 6-bit multiplexed I
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START condition
S
2
C EEPROM DIP switch
Figure 6. Acknowledgement on the I
1
2
8
not acknowledge
acknowledge
8
2
C-bus
9
clock pulse for
acknowledgement
PCA9561
Product data sheet
SW00368