Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 15
Z1601720ASG1868
Manufacturer Part Number
Z1601720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheets
1.Z1601720ASC1868.pdf
(138 pages)
2.Z1601720ASG1868.pdf
(134 pages)
3.Z1601720ASG1868.pdf
(138 pages)
Specifications of Z1601720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PCMCIA Interface Overview
PCMCIA
Interface
PC_A[25:11]
Figure 1.
Power-On Reset
The ZX6017 defaults to the Memory Only interface as outlined in the
PCMCIA specification upon deassertion of Power-On Reset /POR). The
hardware sets Busy on the PC_RDY/BSY pin and then addresses the
EE_MASTER pin. If the EE_MASTER pin is unconnected or pulled
High, the ZX6017 serial interface defaults to the Master mode and an
external EEPROM is required. If this pin is pulled Low, the SLAVE mode
is selected and an external microprocessor is required to configure the
ZX6017 through the serial interface pins.
Next, the hardware addresses the PC_ATA//HOE pin. If the PC_ATA/
HOE pin is held Low for 40 clocks (PC_MCLK_IN) after POR
deassertion, the ZX6017 is enabled for ATA/IDE to ATA/IDE
PASSTHROUGH mode. The PASSTHROUGH mode is for systems that
Attribute Memory
Configuration
ZX6017 Functional Block Diagram
(256 Bytes)
Registers
Address
Decoder
PCMCIA
PCMCIA
Memory
and I/O
(16-Bit)
Z86017/Z16017 PCMCIA Interface Solution
Registers
Control
Peripheral Bus
Interface
Decoder
Window
(16-Bit)
Sequencer
EEPROM
Control
SPI
Reference Manual
RM001102-0901
Peripheral
Local Serial
ATA/IDE
EEPROM
Bus
SPI Port
or
µP
3
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