Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 51
Z1601720ASG1868
Manufacturer Part Number
Z1601720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheets
1.Z1601720ASC1868.pdf
(138 pages)
2.Z1601720ASG1868.pdf
(134 pages)
3.Z1601720ASG1868.pdf
(138 pages)
Specifications of Z1601720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
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EEPROM Register
Address: SELECT 01h
Name: Interrupt Enable Register
Type: Read/Write
Programming Internal Registers
Bit Placement
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Table 13.
Bit Name
EN_PC_INT0
EN_PC_INT1
EN_PC_INT2
EN_PC_INT3
EN_PC_INT4
EN_EXTP_WP
Interrupt Enable Register: Address 01h
Z86017/Z16017 PCMCIA Interface Solution
Description
Enables Local Processor interrupt when PCMCIA host has
written CCR0, the Con•guration Option Register. This
interrupt stays present until this bit is set to 0. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 06h, 2Ch.
Enables Local Processor interrupt when PCMCIA host has
written CCR1, the Card Status Register. This interrupt
stays present until this bit is set to 0. This bit is active when
set to 1. On Power-On Reset, this bit is set to 0. Also see
Registers 06h, 2Ch.
Enables Local Processor interrupt when PCMCIA host has
written CCR2, the Pin Replacement Register. This
interrupt stays present until this bit is set to 0. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 06h, 2Ch.
Enables Local Processor interrupt when PCMCIA host has
written CCR3, the Socket and Copy Register. This
interrupt stays present until this bit is set to 0. This bit is
active when set to 1. On Power-On Reset, this bit is set to
0. Also see Registers 06h, 2Ch.
Enables Local Processor interrupt when ATA_IREQ is
asserted. This interrupt stays present until this bit is set to
0. This bit is active when set to 1. On Power-On Reset, this
bit is set to 0. Also see Registers 06h, 2Ch.
Enables external write protect pin as an input when set to
1. When set to 0, this bit is DASP on the local AT bus side.
On Power-On Reset, this bit is set to 0.
Reference Manual
RM001102-0901
37
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