74HCT4020BQ,115 NXP Semiconductors, 74HCT4020BQ,115 Datasheet
74HCT4020BQ,115
Specifications of 74HCT4020BQ,115
Related parts for 74HCT4020BQ,115
74HCT4020BQ,115 Summary of contents
Page 1
Rev. 03 — 20 January 2010 1. General description The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4020B series. They are specified in compliance with JEDEC standard no. ...
Page 2
... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range −40 °C to +125 °C 74HC4020PW 74HCT4020PW −40 °C to +125 °C 74HC4020BQ 74HCT4020BQ 5. Functional diagram Fig 1. Functional diagram Fig 2. Logic symbol 74HC_HCT4020_3 Product data sheet …continued Name Description TSSOP16 plastic thin shrink small outline package; 16 leads; ...
Page 3
... NXP Semiconductors Fig 4. Logic diagram 6. Pinning information 6.1 Pinning 74HC4020 74HCT4020 1 Q11 Q12 2 Q13 GND 8 Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin Q0 Q13 13, 12, 14, 15 GND 74HC_HCT4020_3 Product data sheet Q10 14 Q9 ...
Page 4
... NXP Semiconductors 7. Functional description Table 3. Function table Input CP ↑ ↓ HIGH voltage level LOW voltage level don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. [1] 7.1 Timing diagram CP input MR input Q10 Q11 Q12 Q13 Fig 7. Timing diagram 74HC_HCT4020_3 Product data sheet ...
Page 5
... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...
Page 6
... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC4020 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage = −20 μ −20 μ −20 μ −4.0 mA −5.2 mA; V ...
Page 7
... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current 5 ΔI additional supply current other inputs 4 5 pin MR pin CP C input I capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see ...
Page 8
... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions t pulse width CP HIGH or LOW; W see Figure HIGH; see recovery time MR to CP; see rec maximum see Figure 8 max frequency V = 2.0 V ...
Page 9
... NXP Semiconductors Table 7. Dynamic characteristics GND (ground = 0 V unless otherwise specified; for test circuit, see L Symbol Parameter Conditions f maximum see Figure 8 max frequency power PD dissipation capacitance [ the same as t and PHL PLH [ the same as t and THL TLH [ used to determine the dynamic power dissipation (P PD × ...
Page 10
... NXP Semiconductors Qn+1 output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 9. Waveforms showing the output Qn to output Qn+1 propagation delays Table 8. Measurement points Type 74HC4020 74HCT4020 74HC_HCT4020_3 Product data sheet ...
Page 11
... NXP Semiconductors Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance. L Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input V I 74HC4020 V CC 74HCT4020 3 V 74HC_HCT4020_3 Product data sheet ...
Page 12
... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
Page 13
... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 14
... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 13. Package outline SOT338-1 (SSOP16) ...
Page 15
... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 16
... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 17
... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74HC4020BQ, 74HCT4020BQ (DHVQFN16 / SOT763-1 package). ...
Page 18
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 19
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Package outline ...