BD8314NUV-E2 Rohm Semiconductor, BD8314NUV-E2 Datasheet - Page 11

• Manufacturer Part Number: BD8314NUV-E2
• Description: IC SWITCHING REG W/MOSFET SON10
• Manufacturer: Rohm Semiconductor
• Series: -r
• Type: Step-Up (Boost), PWMr

Specifications of BD8314NUV-E2

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 4 V ~ 12 V
• Current - Output: 2.5A
• Frequency - Switching: 1.2MHz
• Voltage - Input: 3 V ~ 12 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-VFDFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

BD8314NUV
© 2010 ROHM Co., Ltd. All rights reserved.
www.rohm.com
(4) DC/DC converter frequency response adjustment system
Condition for stable application
The condition for feedback system stability under negative feedback is that the phase delay is 135 °or less when
gain is 1 (0 dB).
Since DC/DC converter application is sampled according to the switching frequency, the bandwidth GBW of the
whole system (frequency at which gain is 0 dB) must be controlled to be equal to or lower than 1/10 of the switching
frequency.
In summary, the conditions necessary for the DC/DC converter are:
- Phase delay must be 135°or lower when gain is 1 (0 dB).
- Bandwidth GBW (frequency when gain is 0 dB) must be equal to or lower than 1/10 of the switching frequency.
To satisfy above two items, R
[1] R
BD8314NUV incorporates phase compensation devices of
R4=62 kΩ and C2=200pF. These C2 and R
values decide the prim ary pole that determines the
bandwidth of DC/DC converter.
Primary pole point frequency
DC/DC converter DC Gain
By Equations (1) and (2), the frequency f
primary pole point is as shown below.
It is recommended that f
kHz. By this setting, R
Therefore, if an appropriate resistance value is not available and routing may cause noise, the use of R
easy setting.
DC
fp
f
SW
1

, R
Gain

2
π
2
fp
, R




A

3
DC

A




R
Gain
R
B
1
1
1



R
R
1
V
2

2
OUT

2
V
π
R
OUT
1
3

C
sw
and R



2
V
1

should be approx.10 kHz. When load response is difficult, it may be set at approx. 20
, R

IN
C



2
2
R
R



・・・・(2)
2
, R
1
1
, which determine the voltage value, will be in the order of several hundred kΩ.
1



3
I
R
R
, D
OUT
2
2
S


and R
R
R
3
sw
ESR




of point 0 dB under limitation of the bandwidth of the DC gain at the
S
1
, R
B
1
in Fig. 34 should be set as follows.
11/15
・・・・(1)
2

, and R
V
OUT
V
OUT

3
V
IN
VOUT
・・・・(3)
R1
R2
Fig.35 Example of phase compensation setting
A
B
V
V
IN
OUT
R3
Rs
Cs
: ERROR AMP Gain
: Oscillator amplification = 0.5
: Input voltage
: Output voltage
About 100dB = 10
Inside of IC
R4
Technical Note
2010.11 - Rev.C
5
C2
3
enables
FB