BA33D15HFP-TR Rohm Semiconductor, BA33D15HFP-TR Datasheet - Page 7

• Manufacturer Part Number: BA33D15HFP-TR
• Description: IC REG LDO 3.3/1.5V 0.5A HRP5
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of BA33D15HFP-TR

• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V, 1.5V
• Voltage - Input: 4.1 V ~ 16 V
• Voltage - Dropout (typical): 0.25V @ 250mA
• Number Of Regulators: 2
• Current - Output: 500mA (Max)
• Current - Limit (min): -
• Operating Temperature: -25°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

●Notes for use
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BA3258HFP,BA33D15HFP,BA33D18HFP
www.rohm.com
10) Overcurrent protection circuit
11) Damage to the internal circuit or element may occur when the polarity of the Vcc pin is opposite to that of the other pins in
1) Absolute maximum ratings
2) GND voltage
3) Thermal Design
4) Inter-pin shorts and mounting errors
5) Actions in strong electromagnetic field
6) Testing on application boards
7) Regarding input pin of the IC
8) Ground Wiring Pattern
9) Thermal Shutdown Circuit (TSD)
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break
down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated
values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
The potential of GND pin must be minimum potential in all operating conditions.
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.
This IC incorporates a built-in thermal shutdown circuit for protection against thermal destruction. Should the junction
temperature (Tj) reach the thermal shutdown ON temperature threshold, the TSD will be activated, turning off all output
power elements. The circuit will automatically reset once the chip's temperature Tj drops below the threshold temperature.
Operation of the thermal shutdown circuit presumes that the IC's absolute maximum ratings have been exceeded.
Application designs should never make use of the thermal shutdown circuit.
An overcurrent protection circuit is incorporated in order to prevention destruction due to short-time overload currents. Continued
use of the protection circuits should be avoided. Please note that the current increases negatively impact the temperature.
applications. (I.e. Vcc is shorted with the GND pin while an external capacitor is charged.) Use a maximum capacitance of
1000 mF for the output pins. Inserting a diode to prevent back-current flow in series with Vcc or bypass diodes between
Vcc and each pin is recommended.
Diode for preventing back current flow
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Fig32 Bypass diode
Bypass diode
VCC
Output pin
P substrate
（Pin A）
（端子 A）
P 基板
N
P
＋
Resistor
抵抗
N
7/8
P
GND
Fig. 33 Example of Simple Bipolar IC Architecture
Parasitic elements
寄生素子
P
＋
N
（端子 B）
（Pin B）
N
P
＋
C
Transistor (NPN)
トランジスタ(NPN)
B
Ｎ
N
N
E
x
Ｐ
P
GND
P 基板
N
P
＋
Ｎ
(Pin B)
GND
(Pin A)
Technical Note
2011.03 - Rev.B
GND
B
E
C
GND
Parasitic elements
Parasitic elements or
transistors