SEH01G72A1BH1MT-30R Swissbit NA Inc, SEH01G72A1BH1MT-30R Datasheet - Page 7

• Manufacturer Part Number: SEH01G72A1BH1MT-30R
• Description: DRAM DDR2 VLP 1GB 244-MINI DIMM
• Manufacturer: Swissbit NA Inc
• Series: -r

Specifications of SEH01G72A1BH1MT-30R

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 667MHz
• Features: -
• Package / Case: 244-MDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1045

I
(0° C ≤ T
Swissbit AG
Industriestrasse 4 – 8
CH – 9552 Bronschhofen
DD
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
t
HIGH between valid commands;
DQ inputs changing once per clock cycle; Address
and control inputs changing once every two clock
cycles
OPERATING CURRENT*) :
One device bank; Active-Read-Precharge;
I
t
t
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as I
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
t
bus inputs are not changing; DQ’s are floating at V
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
t
All Control and Address bus inputs are not changing;
DQ’s are floating at V
PRECHARGE STANDBY CURRENT:
All device banks idle;
t
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing
once per clock cycle
ACTIVE POWER-DOWN
CURRENT:
All device banks open; t
(I
and Address bus inputs are not
changing; DQ’s are floating at
V
ACTIVE STANDBY CURRENT:
All device banks open; t
t
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing
once per clock cycle
OPERATING READ CURRENT*) :
All device banks open, Continuous burst reads; One
module rank active; I
AL = 0; t
(I
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
RC
OUT
CK
RCD
CK
CK
CK
RAS
DD
DD
REF
Specifications and Conditions
= t
); CKE is LOW; All Control
); CKE is HIGH, CS# is HIGH between valid
= t
= t
= t
= t
= 0mA; BL = 4, CL = CL (I
= t
= t
RC
CK
CK
CK
CK
CASE
RAS
RCD
(I
CK
(I
(I
(I
(I
DD
DD
DD
DD
DD
MAX (I
(I
≤ + 85° C V
= t
); t
DD
), t
); CKE is LOW; All Control and Address
); CKE is HIGH, CS# is HIGH;
); CKE is HIGH, CS# is HIGH;
CK
CK
); CKE is HIGH, CS# is HIGH between
RC
(I
= t
= t
DD
DD
), t
CK
RC
), t
OUT
DD
REF
(I
(I
RP
RAS
Q = +1.8V ± 0.1V, V
DD
DD
CK
CK
= 0mA; BL = 4, CL = CL (I
= t
); CKE is HIGH, CS# is
), t
= t
= t
= t
RP
RAS
RAS
CK
CK
(I
DD
DD
= t
(I
), AL = 0;
MAX (I
DD
);
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
RAS
Fon: [phone]
Fax: [phone]
),
MIN (I
DD
DD
), t
DD4W
= +1.8V ± 0.1V)
RP
DD
),
Data Sheet
= t
RP
REF
DD
),
I
I
I
I
I
I
I
I
Symbol
DDO
DD1
DD2P
DD2Q
DD2N
DD3P
DD3N
DD4R
www.swissbit.com
eMail: [e-mail]
5300-555
max.
1215
765
900
360
360
270
495
63
90
Rev.1.2
10.06.2010
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Page 7
of 14