SEN02G64C4BF2SA-30WR Swissbit NA Inc, SEN02G64C4BF2SA-30WR Datasheet

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SEN02G64C4BF2SA-30WR

Manufacturer Part Number
SEN02G64C4BF2SA-30WR
Description
DRAM DDR2 2GB 200-SODIMM
Manufacturer
Swissbit NA Inc
Series
-r
Datasheet

Specifications of SEN02G64C4BF2SA-30WR

Memory Type
DDR2 SDRAM
Memory Size
2GB
Speed
667MHz
Features
-
Package / Case
200-SODIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1052-1042
2GB DDR2
200 Pin SO-DIMM
SEN02G64C4BF2SA-25R
2GB PC2-5300 in FBGA Technoloy
RoHS compliant
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Options:
Environmental Requirements:
* The refresh rate has to be doubled when 85°C>T
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Frequency / Latency
DDR2 800 MT/s CL6
DDR2 667 MT/s CL5
DDR2 533 MT/s CL4
module density
2048MB with 16 dies and 2 ranks
Operating temperature (ambient)
Operating Humidity
10% to 90% relative humidity, noncondensing
Standard Grade (T
Grade E
Grade W
Standard Grade
Grade E
Grade W
(T
(T
(T
(T
(T
A
C
A
C
A
C
)
)
)
)
)
)
– SDRAM SO-DIMM
1
if no tolerances specified ± 0.15mm
-40°C to 85°C*
0°C to 85°C*
0°C to 70°C
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
-40°C to 95°C*
-40°C to 85°C
0°C to 95°C*
0°C to 70°C
0°C to 85°C
0°C to 85°C
Marking
C
>95°C
-25
-30
-37
Data Sheet
Features:
200-pin 64-bit Small Outline, Dual-In-Line Double
Data Rate synchronous DRAM Module
Module organization: dual rank 256M x 64
VDD = 1.8V ±0.1V, V
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Gold-contact pad
This module is fully pin and functional compatible to
the JEDEC PC2-6400 spec. and JEDEC- Standard
MO-224. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component SAMSUNG
K4T1G084QF DIE Rev. F
128Mx8 DDR2 SDRAM in FBGA-60 package
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Eight internal device banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 t
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Figure: mechanical dimensions
www.swissbit.com
eMail: info@swissbit.com
DDQ
Rev.1.2
1.8V ±0.1V
CK
1
30.09.2010
Page 1
of 14

Related parts for SEN02G64C4BF2SA-30WR

SEN02G64C4BF2SA-30WR Summary of contents

Page 1

... DDR2 – SDRAM SO-DIMM 200 Pin SO-DIMM SEN02G64C4BF2SA-25R 2GB PC2-5300 in FBGA Technoloy RoHS compliant Options:  Frequency / Latency DDR2 800 MT/s CL6 DDR2 667 MT/s CL5 DDR2 533 MT/s CL4  module density 2048MB with 16 dies and 2 ranks  Standard Grade (T ...

Page 2

... The second 128 bytes are available to the end user. Module Configuration Organization DDR2 SDRAMs used 256M x 64bit 16 x 128M x 8bit (1024Mbit) Timing Parameters Part Number SEN02G64C4BF2SA-25[E/W]R SEN02G64C4BF2SA-30[E/W]R SEN02G64C4BF2SA-37[E/W]R Pin Name A0-9, A11 – A13 A10/AP BA0 – BA2 DQ0 – DQ63 DM0-DM7 DQS0 - DQS7 DQS0# - DQS7# RAS# ...

Page 3

S0#, S1# CK0 – CK1 CK0# – CK1 REF DDSPD SCL SDA SA0 – SA1 ODT0, ODT1 NC Pin Configuration PIN # Front Side PIN # 1 V REF DQ0 ...

Page 4

PIN # Front Side PIN # DQ18 57 DQ19 DQ24 63 DQ25 DM3 69 NC (RESET DQ26 75 DQ27 CKE0 ...

Page 5

FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 SDRAM SODIMM, 2 RANKS AND 16 COMPONENTS Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Data Sheet www.swissbit.com Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com Rev.1.2 30.09.2010 Page ...

Page 6

... When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. ...

Page 7

Parameter & Test Condition OPERATING CURRENT: *) One device bank Active-Precharge CKE is HIGH, CS HIGH between valid commands; DQ inputs changing once ...

Page 8

Parameter & Test Condition OPERATING READ CURRENT: *) All device banks open, Continuous burst reads; One module rank active 0mA OUT ...

Page 9

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DD AC CHARACTERISTICS PARAMETER SYMBOL Clock cycle time ...

Page 10

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DD AC CHARACTERISTICS PARAMETER SYMBOL Min Address and control input hold t IH time CAS# ...

Page 11

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DD AC CHARACTERISTICS PARAMETER SYMBOL ODT power-down exit t AXPD latency ODT enable from MRS ...

Page 12

SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION 0 NUMBER OF SPD BYTES USED 1 TOTAL NUMBER OF BYTES IN SPD DEVICE 2 FUNDAMENTAL MEMORY TYPE 3 NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON 4 ASSEMBLY 5 DIMM HIGHT ...

Page 13

... Rev.1.2 30.09.2010 5300-555 0x20 0x27 0x10 0x17 0x3C 0x1E 0x1E 0x00 0x06 0x3C 0x7F 0x80 0x18 0x22 0x00 0x00 0x12 0x19 0x7F 0xDA 0x00 “SEN02G64C4BF2SA-xx” 0x52 0x00 0x00 0xff *RoHs compl. DDR2-800MHz CL6 Chip Vendor (Samsung) 2 Module Rank Chip Rev. F ...

Page 14

Locations Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Data Sheet Swissbit AG Industriestrasse 4 – – 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D ...

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