MT18HTF12872AZ-667G1 Micron Technology Inc, MT18HTF12872AZ-667G1 Datasheet - Page 11

• Manufacturer Part Number: MT18HTF12872AZ-667G1
• Description: MODULE DDR2 SDRAM 1GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTF12872AZ-667G1

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 667MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10: DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
Table 11: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef83c6d17f
htf18c128_256_512x72az.fm - Rev. C 12/10 EN
Parameter
Operating bank interleave read current: All device banks interleaving reads; I
= 0mA; BL = 4, CL = CL (I
(I
commands; Address bus inputs are stable during deselects; Data bus inputs are switch-
ing
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
puts are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
RCD (I
CK (I
RP (I
DD
DD
),
),
DD
DD
t
t
RRD =
RAS =
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
),
t
RP =
t
t
RAS MIN (I
RRD (I
t
RP (I
t
CK =
DD
DD
DD
Notes:
DD
),
Specifications and Conditions – 1GB (Die Revision G) (Continued)
Specifications and Conditions – 2GB (Die Revisions E and G)
DD
t
DD
t
DD
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
RCD =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
), AL =
DD
1. Value calculated as one module rank in this operating condition; all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
t
),
RCD (I
t
t
in I
RC =
RCD (I
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM UDIMM
t
CK =
DD2P
DD
t
RC (I
DD
); CKE is HIGH, S# is HIGH between valid
t
(CKE LOW) mode.
CK (I
) - 1 ×
DD4W
DD
),
DD
t
t
),
RAS =
CK (I
t
CK =
t
RAS =
t
CK =
t
CK =
DD
t
t
CK =
t
RAS MIN (I
CK (I
);
t
t
OUT
t
CK (I
CK =
t
t
RAS MAX (I
t
CK (I
CK =
CK =
11
DD
= 0mA; BL = 4, CL
DD
),
t
DD
CK (I
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
CK (I
),
t
CK (I
); CKE is
RAS =
DD
t
RC =
DD
),
DD
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
),
t
),
); CKE
t
RAS
RC
t
t
RC =
RP =
t
RC
Symbol
OUT
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
DD2P
DD3P
DD0
DD1
1
1
Symbol
2
2
2
2
2
1
I
DD7
-1GA
1098
1233
1080
1080
1260
1953
1
126
900
180
© 2009 Micron Technology, Inc. All rights reserved.
IDD Specifications
-80E/
-800
1413
-80E/
-800
1053
1080
1503
873
126
900
900
720
180
1323
-667
1278
-667
828
963
126
720
720
540
180
990
Units
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA