MT18HTF12872AZ-667G1 Micron Technology Inc, MT18HTF12872AZ-667G1 Datasheet - Page 13

• Manufacturer Part Number: MT18HTF12872AZ-667G1
• Description: MODULE DDR2 SDRAM 1GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTF12872AZ-667G1

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 667MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 12: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Table 13: DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
PDF: 09005aef83c6d17f
htf18c128_256_512x72az.fm - Rev. C 12/10 EN
Parameter
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
(I
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
puts are switching; Data pattern is same as I
CK (I
RP (I
OUT
RP =
RCD (I
DD
DD
),
),
= 0mA; BL = 4, CL = CL (I
DD
DD
t
t
t
RP (I
RC =
RAS =
DD
DD
DD
OUT
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
),
DD
= 0mA; BL = 4, CL = CL (I
t
t
RP =
RC (I
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
DD
t
RP (I
t
CK =
),
DD
DD
t
RRD =
DD
Notes:
Specifications and Conditions – 2GB (Die Revision H) (Continued)
Specifications and Conditions – 4GB (Die Revision C)
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
t
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
t
RRD (I
DD
DD
t
1. Value calculated as one module rank in this operating condition; all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
), AL = 0;
CK (I
),
t
in I
RC =
DD
DD
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM UDIMM
t
DD
CK =
DD2P
),
), AL =
); REFRESH command at every
t
t
RCD =
RC (I
t
CK =
t
(CKE LOW) mode.
CK (I
DD4W
DD
t
RCD (I
t
t
DD
),
RCD (I
CK (I
t
),
RAS =
t
CK =
t
DD
RAS =
DD
t
CK =
DD
) - 1 ×
),
t
); CKE is HIGH, S# is
t
CK =
t
t
CK (I
RAS MIN (I
RAS =
t
t
OUT
CK (I
RAS MAX (I
13
t
CK (I
DD
= 0mA; BL = 4, CL
t
DD
),
RAS MAX (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
),
DD
RAS =
DD
t
);
RC =
t
RFC (I
),
t
DD
CK =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RCD =
t
),
t
RAS
RC
t
DD
RP =
DD
t
CK
)
),
Symbol
Symbol
I
I
I
I
DD4W
DD3N
I
I
I
I
I
DD3P
DD4R
DD5
DD6
DD7
DD0
DD1
2
2
1
1
1
2
1
2
1
-1GA
-1GA
1458
1413
1683
2313
TBD
TBD
540
180
720
126
© 2009 Micron Technology, Inc. All rights reserved.
IDD Specifications
-80E/
-80E/
-800
1188
1143
1368
1953
-800
TBD
TBD
360
180
594
126
1098
1053
1323
1728
-667
-667
TBD
TBD
270
180
540
126
Units
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA