AD9882KST-100 Analog Devices Inc, AD9882KST-100 Datasheet - Page 16

• Manufacturer Part Number: AD9882KST-100
• Description: IC INTERFACE/DVI 100MHZ 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9882KST-100

• Rohs Status: RoHS non-compliant
• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount

AD9882A
Four programmable registers are provided to optimize the
performance of the PLL. These registers are
1.
2.
3.
4.
Table 10. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Standard
VGA
SVGA
XGA
SXGA
TV Modes
The 12-bit divisor register (Registers 0x01 and 0x02). The
input Hsync frequencies range from 15 kHz to 110 kHz.
The PLL multiplies the frequency of the Hsync signal,
producing pixel clock frequencies in the range of 12 MHz
to 140 MHz. The divisor register controls the exact
multiplication factor. This register can be set to any value
between 221 and 4095. The divide ratio that is actually
used is the programmed divide ratio plus one.
The 2-bit VCO range register (Register 0x03, Bits 6 and 7).
To improve the noise performance of the AD9882A, the
VCO operating frequency range is divided into three
overlapping regions. The VCO range register sets this
operating range. The frequency ranges for the lowest and
highest regions are shown in Table 8.
The 3-bit charge pump current register (Register 0x03,
Bits 3 to 5). This register allows the current that drives the
low-pass loop filter to be varied. The possible current
values are listed in Table 9.
The 5-bit Phase Adjust Register (Register 0x04, Bits 3 to 7).
The phase of the generated sampling clock can be shifted
to locate an optimum sampling point within a clock cycle.
The phase adjust register provides 32 phase-shift steps of
11.25° each. The Hsync signal with an identical phase shift
is available through the HSOUT pin.
Refresh Resolution
640 × 480
800 × 600
1024 × 768
1280 × 1024
480i
480p
720p
1080i
Horizontal Rate (Hz)
60
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
60
60
60
Rev. 0 | Page 16 of 40
Frequency (kHz)
31.500
37.700
37.500
43.300
35.100
37.900
48.100
46.900
53.700
48.400
56.500
60.000
64.000
68.300
64.000
80.000
15.750
31.470
45.000
33.750
Table 8. VCO Frequency Ranges
PV1
0
0
1
Table 9. Charge Pump Current/Control Bits
Ip2
0
0
0
0
1
1
1
1
The coast function allows the PLL to continue to run at the
same frequency, in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as equalization pulses).
This can be used during the vertical sync period, or any other
time that the Hsync signal is unavailable. Also, the polarity of
the Hsync signal can be set through the Hsync polarity bit
(Register 0x10, Bit 6). If not using automatic polarity detection,
the Hsync polarity bit should be set to match the polarity of the
Hsync input signal.
PV0
0
1
0
Ip1
0
0
1
1
0
0
1
1
Pixel Rate (MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
13.500
74.500
27.000
74.500
Pixel Clock Range (MHz)
12–41
41–82
82–140
Ip0
0
1
0
1
0
1
0
1
Current (µA)
50
100
150
250
350
500
750
1500
VCORNGE
00
00
01
10
00
00
00
00
00
01
01
01
01
01
10
10
10
00
01
01
CURRENT
101
101
101
110
101
110
101
101
101
101
110
110
101
101
101
110
001
100
101
101