AD9882KST-100 Analog Devices Inc, AD9882KST-100 Datasheet - Page 8

• Manufacturer Part Number: AD9882KST-100
• Description: IC INTERFACE/DVI 100MHZ 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9882KST-100

• Rohs Status: RoHS non-compliant
• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount

AD9882A
Pin Type
Data Outputs
Data Clock Output
Digital Video Data
Inputs
Digital Video Clock
Inputs
Data Enable
Control Bits
RTERM
HDCP
PIN DESCRIPTIONS OF SHARED PINS BETWEEN
ANALOG AND DIGITAL INTERFACES
HSOUT—Horizontal Sync Output
A reconstructed and phase-aligned version of the video Hsync.
The polarity of this output can be controlled via a serial bus bit.
In analog interface mode, the placement and duration are
variable. In digital interface mode, the placement and duration
are set by the graphics transmitter.
VSOUT—Vertical Sync Output
The separated Vsync from a composite signal or a direct pass-
through of the Vsync input. The polarity of this output can be
controlled via a serial bus bit. The placement and duration in all
modes is set by the graphics transmitter.
SERIAL PORT (2-WIRE)
SDA—Serial Port Data I/O
SCL—Serial Port Data Clock
A0—Serial Port Address Input
For a full description of the 2-wire serial register, refer to the
2-Wire Serial Control Register Detail section.
Mnemonic
RED [7:0]
GREEN [7:0]
BLUE [7:0]
DATACK
R
R
R
R
R
R
R
R
DE
CTL [0:3]
R
DDCSCL
DDCSDA
MCL
MDA
X0+
X0–
X1+
X1–
X2+
X2–
XC+
XC–
TERM
Function
Outputs of Converter Red, Bit 7 is the MSB
Outputs of Converter Green, Bit 7 is the MSB
Outputs of Converter Bue, Bit 7 is the MSB
Data Output Clock for the Analog and Digital
Interface
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
Digital Data Clock True
Digital Data Clock Complement
Data Enable
Decoded Control Bits
Sets Internal Termination Resistance
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
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DATA OUTPUTS
RED—Data Output, Red Channel
GREEN—Data Output, Green Channel
BLUE—Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. These outputs are
shared between the two interfaces and behave in accordance
with the active interface. Refer to the Analog Interface and
Digital Interface sections.
DATACK—Data Output Clock
Just like the data outputs, the data clock output is shared
between the two interfaces. It behaves differently depending on
which interface is active. Refer to the DATACK—Data Output
Clock section to determine how this pin behaves. .
Value
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Pin
Number
92–99
2–9
12–19
85
33
32
36
35
39
38
41
42
86
22–25
28
53
54
81
82
Interface
Both
Both
Both
Both
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital