MT36HTF51272FDZ-80EH1N8 Micron Technology Inc, MT36HTF51272FDZ-80EH1N8 Datasheet
MT36HTF51272FDZ-80EH1N8
Specifications of MT36HTF51272FDZ-80EH1N8
Related parts for MT36HTF51272FDZ-80EH1N8
MT36HTF51272FDZ-80EH1N8 Summary of contents
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... DDR2 SDRAM FBDIMM MT36HTF51272FDZ – 4GB Features • 240-pin, DDR2 fully buffered DIMM (FBDIMM) • Fast data transfer rates: PC2-4200, PC2-5300, or PC2-6400 • 4GB (512 Meg x 72) • 3.2 Gb/s, 4 Gb/s, and 4.8 Gb/s link transfer rates • High-speed, 1.5V differential, point-to-point link be- ...
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... The data sheet for the base device can be found on Micron’s Web site. Notes: 2. All part numbers end with a four-place code (not shown) that designates component, PCB, and AMB revi- sions. Consult factory for current revision codes. Example: MT36HTF51272FDZ-80EH1N8. PDF: 09005aef8409299f htf36c512x72fdz.pdf - Rev. A 06/10 EN ...
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Pin Assignments and Descriptions Table 4: Pin Assignments 240-Pin FBDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol PN3 PN3 ...
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Table 5: Pin Descriptions Symbol Type Description PS[9:0] Input Primary southbound data, positive lines. PS#[9:0] Input Primary southbound data, negative lines. SCK Input System clock input, positive line. SCK# Input System clock input, negative line. SCL Input Serial presence-detect (SPD) ...
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... System Block Diagram Commodity DDR2 DDR2 SDRAM component devices DDR2 component DDR2 component DDR2 component modules AMB • • • DDR2 component DDR2 component DDR2 component DDR2 component SMBus access to buffer registers Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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Functional Block Diagram Figure 3: Functional Block Diagram RS0# RS2# RS1# RS3# DQS0 DQS0# DM0 DM CS# DQS DQS# DM CS# DQS DQS DQ0 DQ DQ1 DQ DQ DQ2 DQ U1 DQ3 DQ4 DQ DQ5 ...
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General Description Micron’s FBDIMM devices adhere to the currently proposed industry specifications for FBDIMMs. The following specifications contain detailed information on FBDIMM de- sign, interfaces, and theory of operation and are listed here for the system designers’ convenience. Refer to ...
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Table 6: I Conditions (Continued) DD Symbol Condition I Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DD_TRAINING DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active I IBIST over ...
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Table 10: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition ...
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Module Dimensions Figure 4: 240-Pin DDR2 FBDIMM 66.68 (2.63) TYP 0.5 (0.02) R (4X 1.5 (0.059) R (4X) U10 U11 U12 2.6 (0.102) D (2X) 5.2 (0.205) TYP 1.25 (0.0492) Pin 1 TYP 1.0 (0.039) TYP 9.9 (0.39) ...
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