AD9887KS-140 Analog Devices Inc, AD9887KS-140 Datasheet - Page 16

• Manufacturer Part Number: AD9887KS-140
• Description: IC INTRFACE ANALOG/DVI 160-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9887KS-140

• Rohs Status: RoHS non-compliant
• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount

AD9887
Standard
VGA
SVGA
XGA
SXGA
UXGA
Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
Ip2
0
0
0
0
1
1
1
1
PV1
0
0
1
1
Table VI. Charge Pump Current/Control Bits
Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
PV0
0
1
0
1
Table V. VCO Frequency Ranges
Ip1
0
0
1
1
0
0
1
1
Resolution
640 × 480
800 × 600
1024 × 768
1280 × 1024
1600 × 1200
Pixel Clock
Range (MHz)
12–35
35–70
70–110
110–140
Ip0
0
1
0
1
0
1
0
1
Rate (Hz)
Refresh
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
85
60
65
70
75
85
Current ( A)
50
100
150
250
350
500
750
1500
K
(MHz/V)
150
150
150
180
VCO
Gain
Horizontal
Frequency
(kHz)
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
91.1
75.0
81.3
87.5
93.8
106.3
3. The 3-Bit Charge Pump Current Register. This register
4. The 5-Bit Phase Adjust Register. The phase of the generated
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table VI.
provides 32 phase-shift steps of 11.25° each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
The COAST allows the PLL to continue to run at the same
frequency, in the absence of the incoming Hsync signal. This
may be used during the vertical sync period, or any other
time that the Hsync signal is unavailable. The polarity of
the COAST signal may be set through the Coast Polarity Bit.
Also, the polarity of the Hsync signal may be set through the
HSYNC polarity Bit. If not using automatic polarity
detection, the HSYNC and COAST polarity bits should
be set to match the Polarity of their respective signals.
Pixel Rate
(MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
157.500
162.000
175.500
189.000
202.500
229.500
VCORNGE
00
00
00
00
00
01
01
01
01
01
10
10
10
10
10
11
10
10
10
10
10
11
CURRENT
101
101
110
110
101
101
101
101
110
110
101
101
101
101
110
110
110
110
110
110
110
110