PDI1394L40BEGA ST-Ericsson Inc, PDI1394L40BEGA Datasheet - Page 43

• Manufacturer Part Number: PDI1394L40BEGA
• Description: IC IEEE 1394 LINK CTRLR 144-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394L40BEGA

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1176; PDI1394L40BE,551; PDI1394L40BE-S

After a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a Link data confirmation (see
1. All other codes are reserved.
Philips Semiconductors
12.6.2.13 Link data confirmation formats
Figure 32) which is used to confirm the transmission to the higher layers. Packets transmitted from the Transmit Request FIFO are confirmed by
a confirmation written into the Receive Request FIFO and packets transmitted from the Transmit Response FIFO are confirmed by a
confirmation written into the Receive Response FIFO.
Outgoing packets and their confirmations are associated by their tLabels. It is the user’s responsibility to assure the uniqueness of active
tLabels.
Table 5. Confirmation codes
NOTE:
12.7 Interrupts
The PDI1394L40 provides a single interrupt line (HIF INTN) for connection to a host controller. Status indications from five major areas of the
device are collected and ORed together to activate HIF INTN. Status from four major areas of the device are collected in five status registers;
LNKPHYINTACK, ITXINTACK, IRXINTACK, ASYINTACK and RDI. At this level, each individual status can be enabled to generate a chip-level
interrupt by activating HIF INTN. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt is
indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be acknowledged.
To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, ASYINTACK or RDI causing the interrupt
status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.
12.7.1 Determining and Clearing Interrupts
When responding to an interrupt event generated by the PDI1394L40, or operating in polled mode, the first register examined is the RDI
register. Since the addition of the RDI register (at 0x0b0), it will be necessary to first interrogate the RDI register independent of the GLOBCSR
register in order to locate the source of an interrupt. Embedded software should be built to perform this function. It is recommended that this
interrogation take place BEFORE the read of the GLOBCSR register is accomplished. The reason for this added step stems from the fact that
none of the other link registers can be accurately read if the link is in power–down mode. If an attempt to read the GLOBCSR is made during
link power–down, a quadlet will be read, but the quadlet data will not be the contents of the GLOBCSR. Once it has been determined that the
interrupt was not a result of a bit setting in the RDI register, the GLOBCSR register should be tested next. The least significant nibble contains
interrupt status bits from general sections of the device; the link layer controller, the AV transmitter, the AV receiver, and the asynchronous
transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all the enabled interrupt status bits in their
section of the AV Link Layer Controller.
Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy
diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication
will automatically clear in the GLOBCSR.
All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.
2000 Dec 15
1394 enhanced AV link layer controller
CODE
D
E
0
1
2
4
16
16
1
DESCRIPTION
Non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete).
Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete
(transaction complete).
Non-broadcast packet transmitted; addressed node returned an acknowledge pending.
Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries
(transaction complete).
Acknowledge data error received (transaction complete).
Acknowledge type error received (transaction complete).
3130
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 32. Request and response confirmation format
39
tLabel
01
1000
SV01051
conf
PDI1394L40
Preliminary specification