PDI1394L40BEGA ST-Ericsson Inc, PDI1394L40BEGA Datasheet - Page 56

• Manufacturer Part Number: PDI1394L40BEGA
• Description: IC IEEE 1394 LINK CTRLR 144-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394L40BEGA

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1176; PDI1394L40BE,551; PDI1394L40BE-S

Philips Semiconductors
13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024
The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is
included in Common Isochronous Packet (CIP) header quadlet 1.
Reset Value 0x00000000
Bit 16..23:
Bit 14..15:
Bit 11..13:
Bit 10:
13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028
The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.
Reset Value 0x00000000
Bit 29..24:
Bit 23..0:
2000 Dec 15
1394 enhanced AV link layer controller
R/W
R/W
R/W
R/W
R/W
R/W
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8).
QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the
specified size. The value QPC must be less than DBS and less than 2
SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.
FMT: Value to be inserted in the FMT field in the AV header.
FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register
(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on
AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits
of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status
Register is unset (=0), the full 24 bits can be set to any application specified value.
31 30
31 30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT
DBS
FDF
FN
52
QPC
SYT
FN
SV01747
SV00281
.
PDI1394L40
Preliminary specification