ISP1563BMGE ST-Ericsson Inc, ISP1563BMGE Datasheet - Page 20

• Manufacturer Part Number: ISP1563BMGE
• Description: IC USB PCI HOST CTRLR 128-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3158; ISP1563BM

Philips Semiconductors
9397 750 14224
Product data sheet
8.2.1.5 Revision ID register
Table 9:
This 1 B read-only register indicates a device-specific revision identifier. The value is
chosen by the vendor. This field is a vendor-defined extension of the Device ID. The
Revision ID register bit description is given in
Table 10:
Legend: * reset value
Bit
12
11
10 to 9 DEVSELT
8
7
6
5
4
3 to 0
Bit
7 to 0 REVID[7:0]
Symbol
Symbol
RTA
STA
[1:0]
MDPE
FBBC
reserved
66MC
CL
reserved
Status register (address 06h) bit description
REVID - Revision ID register (address 08h) bit description
Description
Received Target Abort: This bit must be set by a master device whenever its
transaction is terminated with Target-Abort. All master devices must
implement this bit.
Signaled Target Abort: This bit must be set by a target device whenever it
terminates a transaction with Target-Abort. Devices that never signal
Target-Abort do not need to implement this bit.
DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three
allowable timing to assert DEVSEL#:
00b — Fast
01b — Medium
10b — Slow
11b — Reserved.
These bits are read-only and must indicate the slowest time that a device
asserts DEVSEL# for any bus command, except Configuration Read and
Configuration Write.
Master Data Parity Error: This bit is implemented by bus masters. It is set
when the following three conditions are met:
Fast Back-to-Back Capable: This read-only bit indicates whether the target
is capable of accepting fast back-to-back transactions when the transactions
are not to the same agent. This bit can be set to logic 1, if the device can
accept these transactions; and must be set to logic 0 otherwise.
-
66 MHz Capable: This read-only bit indicates whether this device is capable
of running at 66 MHz.
0 — 33 MHz
1 — 66 MHz.
Capabilities List: This read-only bit indicates whether this device implements
the pointer for a new capabilities linked list at offset 34h.
0 — No new capabilities linked list is available
1 — The value read at offset 34h is a pointer in configuration space to a linked
list of new capabilities.
-
•
•
•
Access
R
The bus agent asserted PERR# itself, on a read; or observed PERR#
asserted, on a write.
The agent setting the bit acted as the bus master for the operation in
which error occurred.
PER (bit 6 in the Command register) is set.
Rev. 01 — 14 July 2005
Value
11h*
Description
Revision ID: This byte specifies the design revision
number of functions.
Table
10.
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
ISP1563
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