ISP1563BMGE ST-Ericsson Inc, ISP1563BMGE Datasheet - Page 70

• Manufacturer Part Number: ISP1563BMGE
• Description: IC USB PCI HOST CTRLR 128-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3158; ISP1563BM

Philips Semiconductors
Table 96:
Address: Value read from func2 of address 10h + 00h
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
CAPLENGTH/HCIVERSION - Capability Registers Length/Host Controller Interface Version Number
register bit allocation
11.3.1 CAPLENGTH/HCIVERSION register
11.3 EHCI controller capability registers
31
23
15
R
R
R
0
0
0
Table 95:
Address: Value read from func0 or func1 of address 10h + 10Ch
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before the operational
registers.
The bit allocation of this 4 B register is given in
Bit
31 to 8
7
6
5
4
3
2
1
0
30
22
14
R
R
R
0
0
0
Symbol
reserved
PARITY
TIMEOUT
AUX_OUT_
FULL
INH_SW
CMD_DATA
FLAG
IN_FULL
OUT_FULL
HceStatus - Host Controller Emulation Status register bit description
29
21
13
R
R
R
0
0
0
Description
-
Parity: This bit indicates parity error on keyboard and mouse data.
Time-out: This bit indicates a time-out.
Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to
logic 1, OUT_FULL is set to logic 1, and the IRQEN bit is set.
Inhibit Switch: This bit reflects the state of the keyboard inhibit switch. If
set, the keyboard is active.
Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to
port 60h and to logic 1 on an I/O write to port 64h.
Flag: Nominally used as a system flag by software to indicate a warm or
cold boot.
Input Full: Except in the case of a Gate A20 sequence, this bit is set to
logic 1 on an I/O write to address 60h or 64h. While this bit is set to
logic 1 and emulation is enabled, an emulation interrupt condition exists.
Output Full: The Host Controller sets this bit to logic 0 on a read of I/O
port 60h. If IRQEN is set, AUX_OUT_FULL determines which IRQ is
activated. While this bit is logic 0 and C_P in HceControl is set to logic 1,
an emulation interrupt condition exists.
Rev. 01 — 14 July 2005
HCIVERSION[15:8]
HCIVERSION[7:0]
28
20
12
R
R
R
0
0
0
reserved
27
19
11
R
R
R
0
0
0
Table
96.
26
18
10
R
R
R
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
25
17
R
R
R
0
0
9
0
ISP1563
70 of 107
24
16
R
R
R
1
0
8
0