PX1011A-EL1/G,551 NXP Semiconductors, PX1011A-EL1/G,551 Datasheet - Page 2

• Manufacturer Part Number: PX1011A-EL1/G,551
• Description: IC PCI-EXPRESS X1 PHY 81-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of PX1011A-EL1/G,551

• Applications: PCI Express MAX to PCI Express PHY
• Interface: IEEE 1149.1
• Voltage - Supply: 1.2 V
• Package / Case: 81-LFBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3247; 935279563551; PX1011A-EL1/G-S

High-performance, low-power operation
The PCI Express standard specifies a maximum transmitter
peak-to-peak jitter of 120 ps. The PX1011 delivers excellent
transmit jitter and receive performance, with a bit error rate of
better than 1x10
The PX1011’s MAC interface is called the NXP PXPIPE interface,
which is an enhanced version of the Intel PIPE standard. The
PXPIPE interface improves performance in off-chip applications
by using a source synchronous clock for transmit and receive
data. The Intel PIPE uses PCLK to synchronize transmit and
receive data, but the NXP PXPIPE uses separate clocks,
thereby simplifying PCB layout. The 8- bit data interface
operates at 250 MHz with SSTL2 signaling that is compatible
with popular FPGA I/O interfaces.
To save power at every stage of operation, the PX1011
supports five modes of power management. Low power
dissipation and a thin, small package let the PX1011 support
new ExpressCard applications, using a sideband WAKE signal
as a wakeup mechanism for the L2 power mode.
The PX1011 provides digital ASICs and low-cost FPGAs with mixed-signal PHY
functionality
Customer-
functions
specific
Highly integrated
Low-cost FPGA
digital ASIC
protocol
PCIe
-12
.
PX1011
PX1011
Express slots
x1 PCI
PX1011’s small package fits into applications of various sizes
Receiver operation
Incoming data enters the PX1011 at the receiver differential
input interface and is converted from small amplitude
differential signals into rail-to-rail digital signals before
being passed to a deserializer circuit. A Carrier Detect circuit
determines whether data is present on the line and passes this
information to the SERDES and PCS. The SERDES deserializes
data into 10-bit parallel data. The PCS detects a 10-bit comma
character (K28.5) from the random data stream, aligning bits
into a 10-byte boundary format. The PCS then applies 8b/10b
decoding to recover 8-bit data. An elastic buffer brings the
resulting data to the right clock domain.
Transmitter operation
During transmission, 8-bit data from the PXPIPE interface
is encoded using an 8b/10b encoding algorithm. Comma
characters (K28.5) are added for byte synchronization at the
receiver end. The redundancy of 8b/10b encoding ensures that
serial data will be DC-balanced to avoid baseline wander in
AC-coupled systems. It also ensures enough data transition for
clock recovery at the receiver end.
Data is serialized and converted into small-amplitude
differential signals. When multiple bits of the same polarity
are transmitted, the second and subsequent bits are
“de-emphasized” – effectively reducing the low-frequency
components at the transmitter. This “transmitter pre-
equalization” allows the received waveform to exhibit less
inter-symbol interference at the receiver end, after its high-
frequency components are attenuated in the transmission
path. Transmitter de-emphasis is an effective way to expand
the receiver eye pattern.
The transmit clock is generated from an on-chip PLL using
a 100-MHz clock reference. The PLL has a relatively high
bandwidth to pass through an optional spread spectrum and
reduces EMI.