ISP1562BEUM ST-Ericsson Inc, ISP1562BEUM Datasheet - Page 25

• Manufacturer Part Number: ISP1562BEUM
• Description: IC USB HOST CTRL HI-SPD 100LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1562BEUM

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1562BE-T; ISP1562BE-T

NXP Semiconductors
Table 30.
Legend: * reset value
ISP1562_2
Product data sheet
Bit
15 to 0 PORTWAKE
Symbol
CAP[15:0]
PORTWAKECAP - Port Wake Capability register (address 62h) bit description
8.2.2.3 PORTWAKECAP register
8.2.3.1 CAP_ID register
8.2.3 Power management registers
Table 29.
Port Wake Capability (PORTWAKECAP) is a 2-byte register used to establish a policy
about which ports are for wake events; see
correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit
position indicates that a device connected below the port can be enabled as a wake-up
device and the port may be enabled for disconnect or connect, or overcurrent events as
wake-up events. This is an information only mask register. The bits in this register do not
affect the actual operation of the EHCI Host Controller. The system-specific policy can be
established by BIOS initializing this register to a system-specific value. The system
software uses the information in this register when enabling devices and ports for remote
wake-up.
Table 31.
The Capability Identifier (CAP_ID) register when read by the system software as 01h
indicates that the data structure currently being pointed to is the PCI power management
data structure. Each function of a PCI device may have only one item in its capability list
with CAP_ID set to 01h. The bit description of the register is given in
FLADJ value
0 (00h)
1 (01h)
2 (02h)
:
31 (1Fh)
32 (20h)
:
62 (3Eh)
63 (3Fh)
Offset
Value read from address 34h + 0h
Value read from address 34h + 1h
Value read from address 34h + 2h
Value read from address 34h + 4h
Value read from address 34h + 6h
Value read from address 34h + 7h
Access
R/W
Value
0007h*
FLADJ value as a function of SOF cycle time
Power Management registers
Description
Port Wake-Up Capability Mask: EHCI does not implement this feature.
Rev. 02 — 1 March 2007
Register
Capability Identifier (CAP_ID)
Next Item Pointer (NEXT_ITEM_PTR)
Power Management Capabilities (PMC)
Power Management Control/Status (PMCSR)
Power Management Control/Status PCI-to-PCI Bridge
Support Extensions (PMCSR_BSE)
Data
Table
SOF cycle time (480 MHz)
59488
59504
59520
:
59984
60000
:
60480
60496
30. Bit positions 15 to 1 in the mask
HS USB PCI Host Controller
Table
© NXP B.V. 2007. All rights reserved.
ISP1562
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