W83L518G Nuvoton Technology Corporation of America, W83L518G Datasheet - Page 18
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W83L518G
Manufacturer Part Number
W83L518G
Description
IC READER MEDIA 48-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet
1.W83L518G.pdf
(25 pages)
Specifications of W83L518G
Applications
*
Interface
*
Voltage - Supply
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Package / Case
-
Mounting Type
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
W83L518G
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
6.7
CR30 (Default 00h)
CR60, CR61 (Both default 00h)
Base address configuration registers: programmable at addresses from 0100h to 0FF8h on 4-byte
boundary. Base address + 0 and base address + 1 are for GPIO1 as direction register and data
register respectively while base address + 2 and base address + 3 are for GPIO2 as direction register
and data register respectively.
CRF0 (GP10 ~ GP17 direction register. Default FFh)
When set to "1", respective GPIO port is programmed as an input port. When set to a "0", respective
GPIO port is programmed as an output port.
CRF1 (GP10 ~ GP17 data register. Default 00h)
If a port is programmed to be an output port, its respective bit can be read/written and output to
respective pin. If a port is programmed to be an input port, its respective bit reflects what is on
respective pin.
CRF2 (GP10 ~ GP17 inversion register. Default 00h)
When set to "1", respective incoming/outgoing port value is inverted. When set to "0", respective
incoming/outgoing port value is the same as in data register.
CRF3 (GP20 ~ GP27 direction register. Default FFh)
When set to "1", respective GPIO port is programmed as an input port. When set to a "0", respective
GPIO port is programmed as an output port.
Bit 1: MS4 output polarity control bit.
Bit 0: MS4 output enable bit.
Logical Device 2 (GPIO)
Bit [7:3]: Reserved.
Bit 2: Individual disable/enable bit for GPIO2.
Bit 1: Individual disable/enable bit for GPIO1.
Bit 0: Logical device disable/enable bit.
0: MS4 output low.
1: MS4 output high.
0: MS4 output disable.
1: MS4 output enable.
= 0
= 1
= 0
= 1
= 0
= 1
GPIO1 and GPIO2 are disabled/enabled dependent on bit 1 and 2
respectively.
Activates GPIO1 and GPIO2.
GPIO2 is disabled if bit 0 is also "0".
GPIO2 is enabled.
GPIO1 is disabled if bit 0 is also "0".
GPIO1 is enabled.
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W83L518D