W83L518G Nuvoton Technology Corporation of America, W83L518G Datasheet - Page 6

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W83L518G

Manufacturer Part Number
W83L518G
Description
IC READER MEDIA 48-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83L518G

Applications
*
Interface
*
Voltage - Supply
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Package / Case
-
Mounting Type
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W83L518G
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
4. PIN DESCRIPTION
Note:
IN t
IN tp3
IN ts
IN tsp3 - 3.3V TTL level Schmitt-trigger input pin
I/O 12t - 5V TTL level bi-directional pin with 12 mA drive-sink capability
I/O 24t - 5V TTL level bi-directional pin with 24 mA drive-sink capability
I/O 16tp3
O 2
O 12
O 16p3 - 3.3V output pin with 16 mA drive-sink capability
OD 12p3
4.1
LFRAME#
SYMBOL
RESET#
SERIRQ
PCICLK
LDRQ#
PME#
LAD0
LAD1
LAD2
LAD3
Bus Interface
- 5V TTL level input pin
- 3.3V TTL level input pin
- 5V TTL level Schmitt-trigger input pin
- 5V output pin with 2 mA drive-sink capability
- 5V output pin with 12 mA drive-sink capability
- 3.3V TTL level bi-directional pin with 16 mA drive-sink capability
- 3.3V Open-drain output pin with 12 mA sink capability.
PIN
48
47
46
45
44
5
4
3
2
1
I/O
I/O
I/O
I/O
I/O
OD
IN
IN
O
In
I/O
16p3
tsp3
16tp3
16tp3
16tp3
16tp3
16tp3
tsp3
tsp3
12p3
Active-low PME event.
Active-low system reset signal.
Active-low signal indicates start of a new LPC frame or
termination of a premature frame.
Encoded DMA Request signal.
PCI clock input of 33 MHz.
Serial IRQ input/output.
This signal combining with other LADx signals communicate
address, control, and data information over the LPC bus between
a host and a peripheral.
This signal combining with other LADx signals communicate
address, control, and data information over the LPC bus between
a host and a peripheral.
This signal combining with other LADx signals communicate
address, control, and data information over the LPC bus between
a host and a peripheral.
This signal combining with other LADx signals communicate
address, control, and data information over the LPC bus between
a host and peripherals.
- 4 -
FUNCTION
W83L518D

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