AN983BX-BG-T-V1 Infineon Technologies, AN983BX-BG-T-V1 Datasheet - Page 74

• Manufacturer Part Number: AN983BX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BXBGTV1; AN983BXBGTV1XP; SP000075554

Field
ATS
PPE
PCI_R
PS
4_3L
RFS
CRD
PM
APM
LWS
Res
Data Sheet
Bits
27
26
25
24
23
22:21
20
19
18
17
16:8
Type
rw
rw
rw
rw
rw
rw
rw
ro
rw
rw
ro
Description
Actively Type Select
PMEP, This bit is only active when PMEP enable CSR18 bit 26
0
1
PMEP Pin Enable
0
1
PCI_Reset
PWRS_clr
1
Pmes_Sticky
0
1
4_3LED
If this bit is reset, 3 LED mode is selected, the LEDs definition is:
100/10 speed
Link/Activity
Full Duplex/Collision
If this bit is set, 4 LED mode is selected, the LEDs definition is:
100 Link
10 Link
Activity
Full Duplex/Collision
Receive FIFO Size Control
00
01
10
11
Clock Run (clk-run pin) Disable
1
Power Management
Enables the AN983B/BX whether to activate the Power Management
abilities. When this bit is set into “0” the AN983B/BX will set the Cap_Ptr
register to zero, indicating no PCI compliant power management
capabilities.The value of this bit will be mapped to NC-bit 20 of CR1.In
PCI Power Management mode, the Wake-up events include “Wake-up
Frame Received”, “Magic Packet Received” and “Link Status Changed”
depends on the CSR13 settings.
APM Mode
This bit is effective when PM (csr18 [19]) = 1.
0
1
Should be 0
Reserved
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
B
B
B
B
B
B
B
B
up event it will be de-asserted by power up automatically
cannot be auto de-asserted. The software should clear CR49<15>
PMES bit to de-assert the pmez signal.
, reserved
, reserved
, create a positive 50 ms pulse
, create a negative 50 ms pulse
, disable (this pin will be input, to compatible with AN983 circuit)
, enable
, rising will automatically reset CR49/ PWRS[1:0] to 00h
, pmez auto de-asserted: While pmez signal is asserted by wake
, pmez sticky: While pmez signal is asserted by wake up event it
, 2K
, 1K
, disables the function of clock run supports to PCI
, Magic Packet wake-up event default disable
, Magic Packet wake-up event default enable
74
Rev. 1.81, 2005-12-15
AN983B/BX