DC1245A Linear Technology, DC1245A Datasheet - Page 16

• Manufacturer Part Number: DC1245A
• Description: BOARD DEMO LTM4616
• Manufacturer: Linear Technology
• Series: µModuler

Specifications of DC1245A

• Design Resources: LTM4616 Spice Model LTM4616 Gerber Files DC1245 Design Files
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Power - Output: -
• Voltage - Output: 1.2V, 1.8V
• Current - Output: 8A, 8A
• Voltage - Input: 2.7 ~ 5.5 V
• Regulator Topology: Buck
• Frequency - Switching: 1.5MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LTM4616
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. R
slower than MR. Make sure that the slave supply slew rate
is chosen to be fast enough so that the slave output voltage
will reach it final value before the master output.
For example: MR = 3.3V/ms and SR = 1.5V/ms. Then
R
LTM4616
range from 0V to 0.596V. The master’s TRACK pin slew
rate is directly equal to the master’s output slew rate in
Volts/Time:
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R
is equal to 10k. R
where V
tor and V
top feedback resistor of the slave regulator in coincident
tracking, then R
Therefore R
6 shows the output voltage for coincident tracking.
16
applications inForMation
TB
R
MR
SR
= 22.1k. Solve for R
TA
• 10k = R
=
FB
Figure 6. Output Voltage Coincident Tracking
TRACK
10k
is the feedback voltage reference of the regula-
V
FB
TB
= 10k and R
+
is 0.596V. Since R
TA
TB
0.596V
R
V
TA
FB
FB
is equal to R
is derived from equation:
–
V
TA
TB
TRACK
R
TIME
to equal to 4.87k.
TA
TB
can be solved for when SR is
= 6.65k in Figure 5. Figure
MASTER OUTPUT
SLAVE OUTPUT
FB2
TB
with V
is equal to the 10k
4616 F06
FB
= V
TRACK
TB
.
For applications that do not require tracking or sequencing,
simply tie the TRACK pin to SV
turn on/off. Connecting TRACK to SV
~100µs of internal soft-start during start-up.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point. As shown
in Figure 20, the sequencing function can be realized in a
dual output application by controlling the RUN pins and the
PGOOD signals from each other. The 1.5V output begins
its soft starting after the PGOOD signal of 3.3V output
becomes high, and 3.3V output starts its shutdown after
the PGOOD signal of 1.5V output becomes low. This can
be applied to systems that require voltage sequencing
between the core and sub-power supplies.
Stability Compensation
The module has already been internally compensated
for all output voltages. Table 2 is provided for most ap-
plication requirements. LTpowerCAD is available for fine
adjustments to the control loop.
Output Margining
For a convenient system stress test on the LTM4616’s
output, the user can program each output to ±5%, ±10%
or ±15% of its normal operational voltage. Margining
can be disabled by connecting the MGN pin to a voltage
divider as shown in Figure 5. When the MGN pin is <0.3V,
it forces negative margining, in which the output voltage
is below the regulation point. When MGN is >V
the output voltage is forced above the regulation point.
The MGN pin with a voltage divider is driven with a small
tri-state gate as shown in Figure 18 for three margin states,
(High, Low, and No Margin). The amount of output voltage
margining is determined by the BSEL pin. When BSEL is
low, it’s 5%. When BSEL is high, it’s 10%. When BSEL is
floating, it’s 15%. When margining is active, the internal
output overvoltage and undervoltage comparators are
disabled and PGOOD remains high.
IN
to let RUN control the
IN
also enables the
IN
– 0.3V,
4616fc